Multi-port, gigabit serdes transceiver capable of automatic fail switchover

• US 20050190690A1
• Filed: 04/29/2005
• Published: 09/01/2005
• Est. Priority Date: 10/29/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Tran, Hoang
• Granted Patent: US 8,385,188 B2
• Time in Patent Office: Days
• US Class Current: 370/216
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving

Abstract

A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the transceiver can connect any of the serial ports to another serial port or to a parallel port. The transceiver further includes a switch, a logic core, and a bus. The switch is selectively coupled to at least a first port and a second port. The switch activates the first port and deactivates the second port based on satisfaction of a condition associated with the first port. The logic core operates the serial and parallel ports, and the bus connects the ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the ports. The ring structure provides efficient communication between the logic core and the ports.

Claims

1. A transceiver, comprising:

a first port;

a second port; and

a switch selectively coupled to the first port and the second port;

wherein the switch activates the second port and deactivates the first port based on satisfaction of a condition associated with the first port.

2. The transceiver of claim 1, wherein the condition is programmable.

3. The transceiver of claim 1, wherein satisfaction of the condition indicates a failure associated with the first port.

4. The transceiver of claim 1, wherein satisfaction of the condition indicates that the data is misaligned at the first port.

5. The transceiver of claim 1, wherein satisfaction of the condition indicates that a number of errors detected at the first port exceeds a threshold.

6. The transceiver of claim 1, whereby the switch enables data to be read at the second port and disables data from being read at the first port.

7. The transceiver of claim 1, whereby the switch enables data to be transmitted at the second port and disables data from being transmitted at the first port.

8. The transceiver of claim 1, further comprising a packet bit error rate tester (BERT) that determines a bit error rate at the first port.

9. The transceiver of claim 1, wherein the first port and the second port are XAUI serial ports.

10. The transceiver of claim 1, wherein the first and second ports convert between a XAUI serial protocol and a XGMII parallel protocol using a XGXS conversion protocol.

11. The transceiver of claim 1, wherein the first port and the second port are serial ports.

12. The transceiver of claim 11, wherein the switch electrically couples a parallel port to the first port or the second port.

13. The transceiver of claim 12, wherein the parallel port is a XGMII parallel port.

14. The transceiver of claim 12, further comprising:

a bus connecting the first port, the second port, and the parallel port;

wherein the bus, the first port, the second port, and the parallel port are on a common substrate.

15. The transceiver of claim 14, wherein the bus is configured to have a ring shape.

16. The transceiver of claim 14, wherein the bus is a parallel bus.

17. The transceiver of claim 16, wherein the parallel bus includes multiple transmission lines having substantially same length.

18. A method of performing automatic fail switchover in a transceiver having a first port and a second port, the method sequentially comprising:

configuring the first port to be active;

satisfying a condition associated with the first port; and

activating the second port and deactivating the first port.

19. The method of claim 18, wherein satisfying the condition indicates an error associated with the first port.

20. The method of claim 18, wherein activating the second port includes enabling data to be transmitted at the second port, and wherein deactivating the first port includes disabling data from being transmitted at the first port.

21. The method of claim 18, wherein activating the second port includes enabling data to be read at the second port, and wherein deactivating the first port includes disabling data from being read at the first port.