System and method of providing mask defect printability analysis

• US 20050190957A1
• Filed: 01/25/2005
• Published: 09/01/2005
• Est. Priority Date: 03/20/2001
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Pang, Linyong, Karklin, Linard, Cai, Lynn
• Granted Patent: US 7,254,251 B2
• Time in Patent Office: Days
• US Class Current: 382/141
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: Y10T 428/24802 Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]

Abstract

A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information regarding defect printability. Certain other aspects of the mask relating to mask quality, such as line edge roughness and contact corner rounding, can also be quantified by using the simulated wafer image of the physical mask.

Claims

1. A physical mask comprising:

at least one defect being modified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided from analyzing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.

7. The physical mask of claim 1, further including at least one defect being unmodified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided from analyzing the simulated wafer images of the physical mask and the reference mask.

2. A physical mask comprising:

at least one irregularity being modified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided from analyzing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.

10. The physical mask of claim 2, further including at least one irregularity being unmodified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided from analyzing the simulated wafer images of the physical mask and the reference mask.

3. A physical mask comprising:

at least one feature being modified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided by comparing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.

13. The physical mask of claim 3, further including at least one feature being unmodified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided by comparing the simulated wafer images of the physical mask and the reference mask.

4. An integrated circuit fabricated using a physical mask comprising:

at least one feature being modified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided by comparing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.

16. The integrated circuit of claim 4, wherein the physical mask further includes at least one feature being unmodified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided by comparing the simulated wafer images of the physical mask and the reference mask.

5. A physical mask comprising:

at least one defect being unmodified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided from analyzing a simulated wafer image of the physical mask and a simulated wafer image of the reference mask, the reference mask corresponding to a defect-free physical mask.

6. The physical mask of claim 5, further including at least one defect being modified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided from analyzing the simulated wafer images of the physical mask and the reference mask.

9. The physical mask of claim 6, further including at least one irregularity being modified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided from analyzing the simulated wafer images of the physical mask and the reference mask.

8. A physical mask comprising:

at least one irregularity being unmodified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided from analyzing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.

11. A physical mask comprising:

at least one feature being unmodified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided by comparing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.

12. The physical mask of claim 11, further including at least one feature being modified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided by comparing the simulated wafer images of the physical mask and the reference mask.

14. An integrated circuit fabricated using a physical mask comprising:

at least one feature being unmodified based on a first average critical dimension deviation and a first maximum critical dimension deviation provided by comparing a simulated wafer image of the physical mask and a simulated wafer image of a reference mask, the reference mask corresponding to a defect-free physical mask.

15. The integrated circuit of claim 14, wherein the physical mask further includes at least one feature being modified based on a second average critical dimension deviation and a second maximum critical dimension deviation provided by comparing the simulated wafer images of the physical mask and the reference mask.