Integrated circuit packaging using electrochemically fabricated structures

• US 20050191786A1
• Filed: 01/03/2005
• Published: 09/01/2005
• Est. Priority Date: 12/31/2003
• Status: Abandoned Application

• Current Assignee: Microfabrica Incorporated (Technoprobe S.P.A.)
• Original Assignee: Microfabrica Incorporated (Technoprobe S.P.A.)
• Inventors: Cohen, Adam L., Lockard, Michael S., Arat, Vacit
• Application Number:
  US11/029,185
• Publication Number:
  US 20050191786A1
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: C23C 18/1605 by masking
• CPC Class Codes: C23C 18/1608 from pretreatment step, i.e. selective pre-treatment
• CPC Class Codes: C23C 18/1651 Two or more layers only obtained by electroless plating
• CPC Class Codes: C25D 1/003 3D structures, e.g. superposed patterned layers
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 5/10 Electroplating with more than one layer of the same or of different metals for bearings C25D7/10
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 being a ball array, e.g. BGA

Abstract

Embodiments of the invention provide a package for holding an integrated circuit or other electronic component and/or a packaged integrated circuit or electronic component which is formed at least in part via an electrochemical fabrication process from a plurality of adhered layers of conductive and dielectric materials.

Claims

1. A fabrication process for fabricating a package for holding an electronic component, comprising:

(a) forming and adhering a layer of material to a previously formed layer and/or to a substrate, wherein the layer comprises a desired pattern of at least one material; and

(b) repeating the forming and adhering operation of (a) a plurality of times to build up a configuration of conductive interconnect elements in a configuration of a desired package, wherein the plurality of layers are adhered to one another and comprise at least one of (i) at least one structural material and at least one sacrificial material or (ii) at least two structural materials one of which is a conductor and one of which is a dielectric.

2. The process of claim 1 wherein the package comprises metal electrodeposited or electroless deposited on a layer by layer basis where the height of at least some layers is set by a planarization operation that planarizes an interconnect material and at least one other material.

3. The process of claim 1 wherein the package comprises vias and traces that coexist on at least some layers.

4. The process of claim 1 wherein the package comprises at least one more coaxial interconnects.

5. The process of claim 1 wherein the package comprises interconnects having traces having at least two different widths.

6. The process of claim 1 wherein the package comprises interconnects comprising vias that have at least two different widths.

7. The process of claim 1 wherein the package comprises interconnects have trace thicknesses that are at least as thick as some planarized thicknesses of a dielectric material.

8. The process of claim 1 wherein the package comprises interconnects having trace thicknesses that are at least as thick as the differential height between some interconnect traces.

9. The process of claim 1 wherein the at least one layer of the package is formed using a process comprising:

patterning a first material, applying a non-planar seed layer, electrodepositing a second material, and trimming off at least a portion of the deposited first material.

10. A fabrication process for fabricating a packaged electronic component, comprising:

providing a substrate having conductive vias;

forming routing elements on the substrate which have first and second ends, where at least some of the first ends are connectable to a first electronic component and at least some of the second ends connect to vias on the substrate; and

attaching the first electronic component to at least some of the first ends.

11. A fabrication process for fabricating a packaged electronic component, comprising:

providing a substrate;

forming routing elements on the substrate which have first and second ends, where at least some of the first ends are connectable to a first electronic component and at least some of the second ends are connectable to a second electronic component; and

attaching the first and second electronic components to the at least some of the first ends and second ends, respectively.