Method and apparatus for initializing dynamic random access memory (DRAM) devices

• US 20050193183A1
• Filed: 04/29/2005
• Published: 09/01/2005
• Est. Priority Date: 03/10/1998
• Status: Abandoned Application

• Current Assignee: Bradley A. May, Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Paul G. Davis, Richard M. Barth, Todd W. Bystrom
• Original Assignee: Bradley A. May, Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Paul G. Davis, Richard M. Barth, Todd W. Bystrom
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A., Davis, Paul G., Bystrom, Todd W., May, Bradley A.
• Application Number:
  US11/119,319
• Publication Number:
  US 20050193183A1
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module comprises a random access memory device having a memory array. The random access memory device includes a first register to store a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address. A second register stores a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data. A storage device stores a plurality of parameter information that pertains to the random access memory device. The first value and the second value is based on at least a first parameter information of the plurality of parameter information.

Claims

1-24. -24. (canceled)

25. A memory module comprising:

a random access memory device having a memory array, the random access memory device including;

a first register to store a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address; and

a second register to store a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data; and

a storage device to store a plurality of parameter information that pertains to the random access memory device, the first value and the second value to be based on at least a first parameter information of the plurality of parameter information.

26. The memory module of claim 25, wherein the memory array includes dynamic memory cells.

27. The memory module of claim 25, wherein the storage device is a serial presence detect.

28. The memory module of claim 25, wherein the plurality of parameter information includes:

information that represents a time to sense a row of the memory device;

information that represents a time between a row access operation of the memory device and a column access operation of the memory device;

information that represents a time between a row access operation of the memory device and a precharge operation of the memory device; and

information that represents a time between a row sense operation applied to a first bank of the memory device and a row sense operation applied to a second bank of the memory device.

29. A system comprising:

a memory device having a memory array, the memory device including;

a first register to store a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address; and

a second register to store a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data; and

a storage area to store a parameter information that pertains to the memory device, the first value and the second value to be derived from the parameter information; and

a memory controller device, coupled to the memory device, the memory controller device to provide the first value and the second value to the memory device.

30. The system of claim 29, wherein the storage area and the memory device are disposed on a memory module.

31. The system of claim 29, wherein the storage area is a serial presence detect.

32. The system of claim 29, wherein the memory controller device receives the parameter information from the integrated circuit device, wherein the parameter information represents a first timing parameter of the memory device in units of time, the memory controller device to convert the parameter information that represents the first timing parameter from units of time to units of clock cycles of a clock signal to derive the first value.

33. The system of claim 29, wherein the parameter information includes:

information that represents a time to sense a row of the memory device;

information that represents a time between a row access operation of the memory device and a column access operation of the memory device;

information that represents a time between a row access operation of the memory device and a precharge operation of the memory device;

information that represents a time between a row sense operation applied to a first bank of the memory device and a row sense operation applied to a second bank of the memory device; and

information that represents a time between a precharge operation applied to a first bank of the memory device and a precharge operation applied to a second bank of the memory device.

34. The system of claim 29, wherein the memory controller is configured in accordance with the parameter information.

35. A memory controller comprising:

an interface to provide a first value and a second value to a memory device, wherein;

the first value is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in a memory array of the memory device, wherein a location of the data is based on the column address; and

the second value is representative of a number of clock cycles of the clock signal to elapse between the access of data sensed from the row of memory cells and the memory device outputting the data.

36. The memory controller of claim 35, wherein the first value and the second value are generated by converting a timing parameter information of the memory device from units of time to units of clock cycles of the clock signal.

37. The memory controller of claim 35, wherein the memory controller is configured in accordance with parameter information pertaining to the first value and the second value.

38. The memory controller of claim 35, wherein the memory controller is configured in accordance with an information pertaining to a time to sense a row of the memory device.

39. The memory controller of claim 35, wherein the memory controller is configured in accordance with an information pertaining to a time between a row access operation of the memory device and a column access operation of the memory device.

40. The memory controller of claim 35, wherein the memory controller is configured in accordance with an information pertaining to a time between a row access operation of the memory device and a precharge operation of the memory device.

41. The memory controller of claim 35, wherein the memory controller is configured in accordance with an information pertaining to a time between a row sense operation applied to a first bank of the memory device and a row sense operation applied to a second bank of the memory device.

42. The memory controller of claim 35, wherein the memory controller is configured in accordance with an information pertaining to a time between a precharge operation applied to a first bank of the memory device and a precharge operation applied to a second bank of the memory device.

43. A system comprising:

a storage location to store an information representing a plurality of timing parameters pertaining to a random access memory device having a memory array, wherein the information includes information representing a first timing parameter and information representing a second timing parameter;

an integrated circuit device to generate;

a first value from the information representing the first timing parameter, such that the first value is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address; and

a second value from the information representing the second timing parameter, such that the second value is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data.

44. The system of claim 43, wherein the integrated circuit device generates the first value by converting the information representing the first timing parameter from units of time to units of clock cycles of the clock signal, and the integrated circuit device generates the second value by converting the information representing the second timing parameter from units of time to units of clock cycles of the clock signal.

45. The system of claim 44, wherein converting the information representing the first timing parameter further includes dividing a time period of the first timing parameter by a period of the clock signal.

46. The system of claim 43, wherein the storage location is included along with the random access memory device on a memory module.

47. The system of claim 43, wherein the storage location is included in a serial presence detect.

48. The system of claim 43, further including a plurality of registers to store the information, wherein the information includes:

information that represents a time to sense a row of the random access memory device;

information that represents a time between a row access operation of the random access memory device and a column access operation of the random access memory device;

information that represents a time between a row access operation of the random access memory device and a precharge operation of the random access memory device;

information that represents a time between a row sense operation applied to a first bank of the random access memory device and a row sense operation applied to a second bank of the random access memory device; and

information that represents a time between a precharge operation applied to a first bank of the random access memory device and a precharge operation applied to a second bank of the random access memory device.