Method and apparatus for initializing dynamic random access memory (DRAM) devices
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Abstract
A memory module comprises a random access memory device having a memory array. The random access memory device includes a first register to store a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address. A second register stores a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data. A storage device stores a plurality of parameter information that pertains to the random access memory device. The first value and the second value is based on at least a first parameter information of the plurality of parameter information.
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Citations
48 Claims
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1-24. -24. (canceled)
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25. A memory module comprising:
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a random access memory device having a memory array, the random access memory device including;
a first register to store a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address; and
a second register to store a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data; and
a storage device to store a plurality of parameter information that pertains to the random access memory device, the first value and the second value to be based on at least a first parameter information of the plurality of parameter information. - View Dependent Claims (26, 27, 28)
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29. A system comprising:
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a memory device having a memory array, the memory device including;
a first register to store a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address; and
a second register to store a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data; and
a storage area to store a parameter information that pertains to the memory device, the first value and the second value to be derived from the parameter information; and
a memory controller device, coupled to the memory device, the memory controller device to provide the first value and the second value to the memory device. - View Dependent Claims (30, 31, 32, 33, 34)
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35. A memory controller comprising:
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an interface to provide a first value and a second value to a memory device, wherein;
the first value is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in a memory array of the memory device, wherein a location of the data is based on the column address; and
the second value is representative of a number of clock cycles of the clock signal to elapse between the access of data sensed from the row of memory cells and the memory device outputting the data. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42)
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43. A system comprising:
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a storage location to store an information representing a plurality of timing parameters pertaining to a random access memory device having a memory array, wherein the information includes information representing a first timing parameter and information representing a second timing parameter;
an integrated circuit device to generate;
a first value from the information representing the first timing parameter, such that the first value is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address; and
a second value from the information representing the second timing parameter, such that the second value is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data. - View Dependent Claims (44, 45, 46, 47, 48)
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Specification