System and method for reboot reporting

• US 20050193259A1
• Filed: 02/17/2004
• Published: 09/01/2005
• Est. Priority Date: 02/17/2004
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Martinez, Juan I., Wiginton, Scotty Mark, Swaney, William Paul
• Application Number:
  US10/781,477
• Publication Number:
  US 20050193259A1
• Time in Patent Office: Days
• US Class Current: 714/34
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Abstract

A system and method for reboot reporting or notification is provided. One system embodiment may include, for example, a plurality of computer systems having at least one processor and at least one non-maskable interrupt output, a manager system in circuit communication with the plurality of computer systems and having at least one non-maskable interrupt input associated with the plurality of computer systems.

Claims

1. A method of reboot reporting comprising:

reading a plurality of input lines associated with a plurality of computer systems having a plurality of processors;

generating at least one non-maskable interrupt signal;

outputting the non-maskable interrupt signal to a processor of the plurality of computer systems;

outputting the non-maskable interrupt signal to a manager associated with the plurality of computer systems; and

generating an indication that at least one computer system has a fault condition.

2. The method of claim 1 further comprising associating the non-maskable interrupt signal with at least one computer system of the plurality of computer systems.

3. The method of claim 2 further comprising generating a notice identifying the at least one computer system.

4. The method of claim 3 further comprising redistributing the processing load from the at least one computer system to the remaining plurality of computer systems.

5. The method of claim 1 further comprising counting the number of times the non-maskable interrupt signal is generated.

6. A system for reboot reporting comprising:

a plurality of computer systems having at least one processor and at least one non-maskable interrupt output;

a manager system in circuit communication with the plurality of computer systems and comprising at least one non-maskable interrupt input associated with the plurality of computer systems.

7. The system of claim 6 wherein the plurality of computer systems comprises a plurality of non-maskable interrupt outputs and the manager system comprises a plurality of non-maskable interrupt inputs.

8. The system of claim 7 wherein the non-maskable interrupt outputs of the plurality of computer systems are in circuit communication with the plurality of non-maskable inputs of the manager system.

9. The system of claim 6 wherein the plurality of computer systems comprises at least one computer system having a processor, a first bridge circuit and a second bridge circuit and wherein the second bridge circuit comprising a non-maskable interrupt signal output in circuit communication with the processor.

10. The system of claim 9 wherein the non-maskable interrupt output of the second bridge is in circuit communication with the manager system.

11. The system of claim 6 further comprising logic for reading at least one non-maskable interrupt input associated with the plurality of computer systems.

12. The system of claim 11 further comprising logic for generating an indication that at least one computer system has a fault condition based on the presence of a non-maskable interrupt signal present on the at least one non-maskable interrupt input.

13. A system for reboot reporting comprising:

a plurality of computers;

means for managing the plurality of computers; and

means for outputting a non-maskable interrupt signal indicating a fault condition associated with at least one of the plurality of computers to the means for managing.

14. The system of claim 13 further comprising means for detecting the non-maskable interrupt signal indicating a fault condition associated with at least one of the plurality of computers and generating a detection signal in response thereto.

15. The system of claim 13 further comprising means for generating at least one non-maskable interrupt signal.

16. The system of claim 13 further comprising means for generating an indication that at least one computer has a fault condition.

17. The system of claim 13 further comprising means for associating the non-maskable interrupt signal with at least one computer of the plurality of computers.

18. The system of claim 17 further comprising means for redistributing the processing load from the at least one computer to the remaining plurality of computers.

19. The method of claim 13 further comprising means for counting the number of times the non-maskable interrupt signal is generated.

20. A computer system comprising:

a processor;

a memory;

at least one bridge circuit in circuit communication with the processor;

a non-maskable interrupt signal circuit in circuit communication with the processor and at least one other computer system.

21. The system of claim 21 wherein the at least one other computer system comprises an enclosure manager.

22. A system comprising:

an enclosure having a plurality of individual computer systems and a manager computer system;

wherein at least one of the plurality of computer systems comprises a processor and a non-maskable interrupt signal circuit, the non-maskable interrupt signal circuit in communication with the processor and the manager computer system, the non-maskable interrupt signal circuit comprising a bridge circuit and a non-maskable interrupt signal path to the processor and the manager computer system.

23. The system of claim 22 wherein the manager computer system comprises a non-maskable interrupt signal input.

24. The system of claim 23 wherein the manager computer system comprises logic for reading a state of the non-maskable interrupt signal input.

25. The system of claim 24 wherein the manager computer system comprises logic for generating a notice based on the state of the of the read non-maskable interrupt signal input.

26. A system comprising:

means for housing a plurality of digital devices;

means for managing the plurality of digital devices, said means for managing comprising a location within said means for housing;

means for receiving and processing executable instructions, said means for receiving and processing comprising a location within said means for housing;

means for generating a non-maskable interrupt signal; and

means for communicating the non-maskable interrupt signal to the means for receiving and processing and to the means for managing.

27. The system of claim 26 wherein the means for communicating the non-maskable interrupt signal to the means for receiving and processing and to the means for managing comprising a non-maskable interrupt signal pathway.

28. The system of claim 26 wherein the means for managing the plurality of digital devices comprises means for reading the state of the means for communicating and means for generating a notice based on the state of the means for communicating.

29. The system of claim 26 wherein the means for managing the plurality of digital devices comprises means for redistributing a processing distribution among the plurality of digital devices.

30. The system of claim 26 wherein the means for generating a non-maskable interrupt signal comprises a bridge circuit associated with the means for receiving and processing.