Decoupling the number of logical threads from the number of simultaneous physical threads in a processor

• US 20050193278A1
• Filed: 12/29/2003
• Published: 09/01/2005
• Est. Priority Date: 12/29/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jourdan, Stephan J., Marden, Morris, Farcy, Alexandre J., Michaud, Pierre, Carmean, Douglas M., Hinton, Robert L., Hammarlund, Per H.
• Granted Patent: US 7,797,683 B2
• Time in Patent Office: Days
• US Class Current: 714/47.1
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence

Abstract

Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

Claims

1. A method of managing threads, comprising:

supporting a plurality of logical threads with a plurality of simultaneous physical threads.

2. The method of claim 1, further including maintaining each of the plurality of logical threads in one of a wait state, an active state, a drain state and a stall state.

3. The method of claim 2, wherein a first logical thread is maintained in the active state, the method further including:

mapping macro-instructions associated with the first logical thread to a next instruction pointer of a physical thread; and

monitoring a processor for a triggering event;

holding the first logical thread in the active state until the triggering event is present.

4. The method of claim 3, further including:

halting the mapping if the triggering event is present; and

switching the first logical thread to the drain state.

5. The method of claim 3, wherein the triggering event includes at least one of a memory latency event, a sleep request and a thread priority event.

6. The method of claim 2, wherein a first logical thread is maintained in the drain state, the method further including:

monitoring the first logical thread for an interruptible point; and

holding the first logical thread in the drain state until the interruptible point is encountered.

7. The method of claim 6, further including switching the first logical thread to the stall state if the interruptible point is encountered.

8. The method of claim 6, wherein the interruptible point corresponds to either an end of a macro-instruction in the first logical thread, or a retirement of a last micro-operation associated with the first logical thread.

9. The method of claim 2, wherein a first logical thread is maintained in the stall state, the method further including:

monitoring a processor for a triggering event; and

holding the first logical thread in the stall state until the triggering event is not present.

10. The method of claim 9, further including switching the first logical thread to the wait state if the triggering event is not present.

11. The method of claim 9, further switching the first logical thread to the wait state if another event having a higher priority than the triggering event is signaled.

12. The method of claim 9, wherein the triggering event includes at least one of a memory latency event, a sleep request and a thread priority event.

13. The method of claim 2, wherein a first logical thread is maintained in the wait state, the method further including:

monitoring the plurality of simultaneous physical threads for an available physical thread; and

holding the first logical thread in the wait state until the available physical thread is encountered.

14. The method of claim 13, further including switching the first logical thread to the active state if the available physical thread is encountered.

15. The method of claim 1, further including storing thread information in a thread management table, the thread information identifying a state, one or more triggering events and a linear instruction pointer for each of the plurality of logical threads.

16. The method of claim 15, wherein the thread information further includes a resource requirement profile for each of the plurality of logical threads.

17. The method of claim 1, wherein the plurality of logical threads is greater in number than the plurality of simultaneous physical threads.

18. The method of claim 1, wherein the plurality of logical threads is fewer in number than the plurality of simultaneous physical threads.

19. A method of supporting a plurality of logical threads with a plurality of simultaneous physical threads, comprising:

mapping macro-instructions associated with a first logical thread to a next instruction pointer of a simultaneous physical thread;

monitoring a processor for a triggering event at a first time;

holding the first logical thread in an active state until the triggering event is present;

halting the mapping and switching the first logical thread to a drain state if the triggering event is present;

monitoring the first logical thread for an interruptible point;

holding the first logical thread in the drain state until the interruptible point is encountered;

switching the first logical thread to a stall state if the interruptible point is encountered;

monitoring the processor for the triggering event at a second time;

holding the first logical thread in the stall state until the triggering event is not present;

switching the first logical thread to a wait state if the triggering event is not present;

monitoring the plurality of simultaneous physical threads for an available physical thread;

holding the first logical thread in the wait state until the available physical thread is encountered; and

switching the first logical thread to the active state if the available physical thread is encountered.

20. The method of claim 19, wherein the triggering event includes at least one of a memory latency event, a sleep request and a thread priority event.

21. The method of claim 19, wherein the interruptible point corresponds to either an end of a macro-instruction in the first logical thread, or a retirement of a final micro-operation associated with a first logical thread.

22. The method of claim 19, further including storing thread information in a thread management table, the thread information identifying a state, one or more triggering events and a linear instruction pointer for each of the plurality of logical threads.

23. A thread management architecture comprising:

a state machine to support a plurality of logical threads with a plurality of simultaneous physical threads by maintaining each of the plurality of logical threads in one of a wait state, an active state, a drain state and a stall state.

24. The thread management architecture of claim 23, wherein the state machine is to map macro-instructions associated with a first logical thread to a next instruction pointer of a physical thread, monitor a processor for a triggering event and hold the first logical thread in the active state until the triggering event is present.

25. The thread management architecture of claim 23, wherein the state machine is to monitor a first logical thread for an interruptible point and hold the first logical thread in the drain state until the interruptible point is encountered.

26. The thread management architecture of claim 23, wherein the state machine is to monitor a processor for a triggering event and hold a first logical thread in the stall state until the triggering event is not present.

27. The thread management architecture of claim 23, further including a hardware sequencer, the hardware sequencer to monitor the plurality of simultaneous physical threads for an available physical thread, the state machine to hold the first logical thread in the wait state until the available physical thread is encountered.

28. A computer system comprising:

a random access memory to store macro-instructions;

a system bus coupled to the memory; and

a processor coupled to the system bus to retrieve the macro-instructions, the processor including a thread management architecture having a state machine to support a plurality of logical threads that correspond to the macro-instructions with a plurality of simultaneous physical threads by maintaining each of the plurality of logical threads in one of a wait state, an active state, a drain state and a stall state.

29. The computer system of claim 28, wherein the state machine is to map macro-instructions associated with a first logical thread to a next instruction pointer of a physical thread, monitor the processor for a triggering event and hold the first logical thread in the active state until the triggering event is present.

30. The computer system of claim 28, wherein the state machine is to monitor a first logical thread for an interruptible point and hold the first logical thread in the drain state until the interruptible point is encountered.

31. The computer system of claim 28, wherein the state machine is to monitor the processor for a triggering event and hold a first logical thread in the stall state until the triggering event is not present.

32. The computer system of claim 28, wherein the thread management architecture further includes a hardware sequencer, the hardware sequencer to monitor the plurality of simultaneous physical threads for an available physical thread that corresponds to a first logical thread, the state machine to hold the first logical thread in the wait state until the available physical thread is encountered.

33. The computer system of claim 28 further including a thread management table to store thread information, the thread information to identify a state, one or more triggering events and a linear instruction pointer for each of the plurality of logical threads.

34. The computer system of claim 33, wherein the thread information is to further identify a resource requirement profile for each of the plurality of logical threads.

35. The computer system of claim 28, wherein the plurality of logical threads is to be greater in number than the plurality of simultaneous physical threads.

36. The computer system of claim 28, wherein the plurality of logical threads is to be fewer in number than the plurality of simultaneous physical threads.