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Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks

  • US 20050193299A1
  • Filed: 02/27/2004
  • Published: 09/01/2005
  • Est. Priority Date: 02/27/2004
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a circuit configured to be tested; and

    a plurality of test blocks within said circuit each comprising (i) a plurality of sequential elements and (ii) a plurality of logic elements, wherein (i) each of said test blocks are configured to operate (a) in a first mode comprising a shift mode and (b) a second mode comprising a capture mode, (ii) said shift mode operates with multiple scan clocks that are clocked simultaneously, and (iii) said capture mode operates with multiple scan clocks with only one of the scan clocks being toggled at a time.

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