System for error correction coding and decoding

• US 20050193312A1
• Filed: 03/01/2004
• Published: 09/01/2005
• Est. Priority Date: 03/01/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Smith, Kenneth Kay, Jedwab, Jonathan, Banks, David, Davis, James A.
• Granted Patent: US 7,418,644 B2
• Time in Patent Office: Days
• US Class Current: 714/755
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/23 using convolutional codes, e.g. unit memory codes
• CPC Class Codes: H03M 13/3707 Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
• CPC Class Codes: H03M 13/3761 using code combining, i.e. using combining of codeword portions which may have been transmitted separately, e.g. Digital Fountain codes, Raptor codes or Luby Transform [LT] codes

Abstract

A system for error correction coding and decoding information is disclosed. In one embodiment, the first and second encoders are each configured to encode the information, wherein the second encoder has a higher capability than the first encoder. First and second decoders are configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information.

Claims

1. A system for error correction coding and decoding information, comprising:

first and second encoders each configured to encode the information, wherein the second encoder has a higher capability than the first encoder; and

first and second decoders configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information.

2. The system of claim 1, wherein the information is encoded to produce a codeword by combining the information, first parity symbols generated when the first encoder encodes the information and second parity symbols generated when the second encoder encodes the information.

3. The system of claim 2, comprising:

a multiplexer configured to combine the information, the first parity symbols and the second parity symbols into the codeword.

4. The system of claim 1, wherein the information is encoded by combining the information, first parity symbols generated when the first encoder encodes the information and second parity symbols generated when the second encoder encodes both the information and the first parity symbols.

5. The system of claim 1, wherein the first decoder is configured to recover the information using first parity symbols generated when the first encoder encodes the information, and provide an indication if the information cannot be recovered.

6. The system of claim 5, wherein the second decoder is configured to recover the information by using second parity symbols generated when the second encoder encodes the information, wherein the second decoder recovers the information only if the first decoder provides the indication.

7. The system of claim 6, wherein the number of the second parity symbols which is greater than a number of the first parity symbols generated by the first encoder.

8. The system of claim 5, wherein the second decoder is configured to recover the information by using second parity symbols generated when the second encoder encodes both the information and the first parity symbols, wherein the second decoder recovers the information only if the first decoder provides the indication.

9. The system of claim 8, wherein the number of the second parity symbols which is greater than a number of the first parity symbols generated by the first encoder.

10. The system of claim 6, wherein the second decoder comprises:

a register configured to store the information and the second parity symbols;

a processor system configured to recover the information by using second parity symbols only if the first decoder provides the indication.

11. The system of claim 1, wherein the first decoder recovers the information by using the first parity symbols to detect and correct any errors in the information.

12. The system of claim 1, wherein the second decoder recovers the information by using the second parity symbols to detect and correct any errors in the information.

13. A storage system having a system for error correction coding and decoding information, comprising:

first and second encoders each configured to encode the information, wherein the second encoder can locate and correct a larger number of errors than the first encoder; and

first and second decoders configured to recover the information, wherein the second decoder recovers the information encoded by the second encoder only if the first decoder cannot recover the information, wherein the first and second encoders and the first and second decoders use a Reed-Solomon code.

14. The system of claim 13, wherein the first and second encoders and the first and second decoders use a linear block code.

15. The system of claim 14, wherein the linear block code is a cyclic redundancy check code.

16. The system of claim 13, wherein the first and second encoders and the first and second decoders use a convolutional code.

17. The system of claim 13, wherein the first and second encoders and the first and second decoders use a burst-correcting code.

18. An error correction coding (ECC) and decoding circuit for detecting and correcting errors in data, comprising:

first ECC encoder circuit configured to generate first parity symbols;

second ECC encoder circuit configured to generate second parity symbols, wherein a number of the second parity symbols is greater than a number of the first parity symbols, and wherein the first parity symbols, the second parity symbols and the data are combined into a codeword;

first ECC decoder circuit configured to decode the codeword by detecting or correcting errors in the data using the first parity symbols; and

second ECC decoder circuit configured to decode the codeword by detecting or correcting the errors in the data using the second parity symbols only if the first ECC decoder circuit cannot detect or correct the errors in the data.

19. The circuit of claim 18, wherein the first ECC encoder circuit generates the first parity symbols from the data.

20. The circuit of claim 18, wherein the second ECC encoder circuit generates the second parity symbols from the data.

21. The circuit of claim 18, wherein the second ECC encoder circuit generates the second parity symbols from both the first parity symbols and the data.

22. A system for error correction coding and decoding information, comprising:

first and second encoder means each configured to encode the information, wherein the second encoder means can locate and correct a larger number of errors than the first encoder means; and

first and second decoder means configured to recover the information, wherein the second decoder means recovers the information encoded by the second encoder means only if the first decoder means cannot recover the information.

23. A method of error correction coding and decoding information, comprising:

generating a number of first parity symbols from the information;

generating a number of second parity symbols from the information, wherein the number of the second parity symbols is greater than the number of the first parity symbols;

combining the first parity symbols, the second parity symbols and the information into an encoded data block;

recovering the information from the encoded data block using the first parity symbols if the information can be recovered using the first parity symbols; and

recovering the information from the encoded data block using the second parity symbols only if the information cannot be recovered using the first parity symbols.

24. The method of claim 23, wherein generating a number of the second parity symbols from the information includes generating the number of the second parity symbols from both the first parity symbols and the information.

25. The method of claim 23, wherein recovering the information from the encoded data block using the first parity symbols includes detecting or correcting errors in the information which can be detected or corrected using the first parity symbols.

26. The method of claim 23, wherein recovering the information from the encoded data block using the second parity symbols includes detecting or correcting errors in the information using the second parity symbols.

27. The method of claim 23, wherein recovering the information from the encoded data block using the second parity symbols includes detecting or correcting errors in the first parity symbols and the information using the second parity symbols.