Method of extraction of wire capacitances in LSI device having diagonal wires and extraction program for same

• US 20050193354A1
• Filed: 07/27/2004
• Published: 09/01/2005
• Est. Priority Date: 02/26/2004
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Watanabe, Jun, Ohba, Hisayoshi
• Granted Patent: US 7,185,296 B2
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method and program for capacitance extraction enabling reduction of the need for division into segments during extraction of capacitances in an LSI device having diagonal wires, so that increases in the number of processes for capacitance extraction can be suppressed are provided. In the method and program, a wire model is generated in which, for a wire segment such that the wire of interest and an adjacent wire are not parallel, either the wire of interest or the adjacent wire is replaced so as to be parallel to the other, and the capacitance of the wire of interest is extracted for this wire model, so that the number of processes in the capacitance extraction process can be reduced.

Claims

1. A wire capacitance extraction method for interconnects in an integrated circuit, comprising:

a wire model generation step of generating wire model data by replacing a wire of interest or a wire adjacent thereto so that both wires become parallel with interval of prescribed distance, for a wire segment, which is included in layout data of said interconnects, and in which the wire of interest and the wire adjacent thereto are not parallel; and

,

a capacitance extraction step of extracting a capacitance value for said wire segment of the wire of interest included in the wire model data, based on said prescribed distance.

2. The wire capacitance extraction method according to claim 1, wherein said wire model generation step has a process of calculating said prescribed distance based on a capacitance value which is obtained by integration from a starting point to an ending point of said wire segment according to a distance between said wire of interest and the adjacent wire.

3. The wire capacitance extraction method according to claim 1, wherein, in said wire model generation step, when there is a portion of said wire segment such that the distance between the wire of interest and the adjacent wire exceeds a prescribed threshold distance, the portion exceeding the threshold distance is replaced by a wire segment having the wire of interest and the adjacent wire being parallel with interval of said threshold distance, and the portion not exceeding said threshold distance is replaced by a wire segment having the wire of interest and the adjacent wire being parallel with interval of said prescribed distance.

4. The wire capacitance extraction method according to claim 1, wherein said layout data has main-axis wires extending in X and Y directions and diagonal wires extending in directions diagonal to the X and Y directions, and when said wire of interest is the main-axis wire and said adjacent wire is the diagonal wire, in said wire model generation step, the adjacent wire is replaced by a main-axis wire to become parallel to said wire of interest.

5. The wire capacitance extraction method according to claim 1, wherein said layout data has main-axis wires extending in X and Y directions and diagonal wires extending in directions diagonal to the X and Y directions, and when said wire of interest is the diagonal wire and said adjacent wire is the main-axis wire, in said wire model generation step, the wire of interest is replaced by a main-axis wire to become parallel to said adjacent wire.

6. The wire capacitance extraction method according to claim 1, wherein said layout data has main-axis wires extending in the X and Y directions and diagonal wires extending in directions diagonal to the X and Y directions, and when both said wire of interest and said adjacent wire are diagonal wires, in said wire model generation step, the wire of interest and said adjacent wire are both replaced by main-axis wires parallel to each other.

7. The wire capacitance extraction method according to claim 1, wherein said capacitance extraction step has a process of referencing a capacitance rule table having capacitance values corresponding to parameters for distance from adjacent wire, and of extracting, as the capacitance value for the wire segment, the capacitance value corresponding to parameter matching to said prescribed distance.

8. A wire capacitance extraction method for interconnects in an integrated circuit, comprising:

a wire model generation step of generating wire model data by replacing diagonal wires which extend in directions diagonal to X and Y directions with main-axis wires which extend in the X and Y directions so as to become parallel with interval of prescribed distance, for a wire segment in which a wire of interest and a wire adjacent thereto are included, in which either the wire of interest and the adjacent wire is said diagonal wire, and which is included in layout data of said interconnects having the main-axis wires and the diagonal wires; and

,

a capacitance extraction step of extracting a capacitance value for said wire segment of the wire of interest included in the wire model data, based on said prescribed distance.

9. The wire capacitance extraction method according to claim 8, wherein said wire model generation step has a process of calculating said prescribed distance based on a capacitance value which is obtained by integration from a starting point to an ending point of said wire segment according to a distance between said wire of interest and the adjacent wire.

10. A wire capacitance extraction program causing a computer to execute a procedure to extract a capacitance value of an interconnect in an integrated circuit, wherein said procedure comprises:

a wire model generation procedure of generating wire model data by replacing a wire of interest or a wire adjacent thereto so that both wires become parallel with interval of prescribed distance, for a wire segment, which is included in layout data of said interconnects, and in which the wire of interest and the wire adjacent thereto are not parallel; and

,

a capacitance extraction procedure of extracting a capacitance value for said wire segment of the wire of interest included in the wire model data, based on said prescribed distance.

11. The wire capacitance extraction program according to claim 10, wherein said wire model generation procedure has a procedure of calculating said prescribed distance based on a capacitance value which is obtained by integration from a starting point to an ending point of said wire segment according to a distance between said wire of interest and the adjacent wire.

12. The wire capacitance extraction program according to claim 10, wherein, in said wire model generation procedure, when there is a portion of said wire segment such that the distance between the wire of interest and the adjacent wire exceeds a prescribed threshold distance, the portion exceeding the threshold distance is replaced by a wire segment having the wire of interest and the adjacent wire being parallel with interval of said threshold distance, and the portion not exceeding said threshold distance is replaced by a wire segment having the wire of interest and the adjacent wire being parallel with interval of said prescribed distance.

13. A wire capacitance extraction program causing a computer to execute a procedure to extract a capacitance value of an interconnect in an integrated circuit, wherein said procedure comprises:

a wire model generation procedure of generating wire model data by replacing diagonal wires which extend in directions diagonal to X and Y directions with main-axis wires which extend in the X and Y directions so as to become parallel with interval of prescribed distance, for a wire segment in which a wire of interest and a wire adjacent thereto are included, in which either the wire of interest and the adjacent wire is said diagonal wire, and which is included in layout data of said interconnects having the main-axis wires and the diagonal wires; and

,

a capacitance extraction procedure of extracting a capacitance value for said wire segment of the wire of interest included in the wire model data, based on said prescribed distance.

14. The wire capacitance extraction program according to claim 13, wherein said wire model generation procedure has a process of calculating said prescribed distance based on a capacitance value which is obtained by integration from a starting point to an ending point of said wire segment according to a distance between said wire of interest and the adjacent wire, in case one of said wire of interest and the adjacent wire of said wire segment is the main-axis wire and the other is the diagonal wire.

15. An integrated circuit logic verification method, comprising:

a wire model generation step of generating wire model data by replacing a wire of interest or a wire adjacent thereto so that both wires become parallel with interval of prescribed distance, for a wire segment, which is included in layout data of said interconnects, and in which the wire of interest and the wire adjacent thereto are not parallel;

a capacitance extraction step of extracting a capacitance value for said wire segment of the wire of interest included in the wire model data, based on said prescribed distance; and

,

a logic verification step of performing logic verification of the integrated circuit by using delay time for said wire of interest calculated based on said extracted capacitance.

16. A logic verification program causing a controller to execute a procedure to perform an integrated circuit logic verification procedure, wherein said procedure comprises:

a wire model generation procedure of generating wire model data by replacing a wire of interest or a wire adjacent thereto so that both wires become parallel with interval of prescribed distance, for a wire segment, which is included in layout data of said interconnects, and in which the wire of interest and the wire adjacent thereto are not parallel;

a capacitance extraction procedure of extracting a capacitance value for said wire segment of the wire of interest included in the wire model data, based on said prescribed distance; and

,

a logic verification procedure of performing logic verification of the integrated circuit by using delay time for said wire of interest calculated based on said extracted capacitance.

17. An integrated circuit logic verification method, comprising:

a wire model generation step of generating wire model data by replacing diagonal wires which extend in directions diagonal to X and Y directions with main-axis wires which extend in the X and Y directions so as to become parallel with interval of prescribed distance, for a wire segment in which a wire of interest and a wire adjacent thereto are included, in which either the wire of interest and the adjacent wire is said diagonal wire, and which is included in layout data of said interconnects having the main-axis wires and the diagonal wires;

a capacitance extraction step of extracting a capacitance value for said wire segment of the wire of interest included in the wire model data, based on said prescribed distance; and

,

a logic verification step of performing logic verification of the integrated circuit by using delay time for said wire of interest calculated based on said extracted capacitance.

18. A logic verification program causing a controller to execute a procedure to perform an integrated circuit logic verification procedure, wherein said procedure comprises:

a wire model generation procedure of generating wire model data by replacing diagonal wires which extend in directions diagonal to X and Y directions with main-axis wires which extend in the X and Y directions so as to become parallel with interval of prescribed distance, for a wire segment in which a wire of interest and a wire adjacent thereto are included, in which either the wire of interest and the adjacent wire is said diagonal wire, and which is included in layout data of said interconnects having the main-axis wires and the diagonal wires;

a capacitance extraction procedure of extracting a capacitance value for said wire segment of the wire of interest included in the wire model data, based on said prescribed distance; and

,

a logic verification procedure of performing logic verification of the integrated circuit by using delay time for said wire of interest calculated based on said extracted capacitance.