Allocation of combined or separate data and control planes

• US 20050193357A1
• Filed: 02/27/2004
• Published: 09/01/2005
• Est. Priority Date: 02/27/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Honary, Hooman, Chen, Inching, Tsui, Ernest T.
• Granted Patent: US 7,424,698 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

Claims

1. A method comprising allocating a plurality of mesh networks for data and control in a heterogeneous reconfigurable device.

2. The method of claim 1 further comprising:

reading a protocol file from a memory; and

configuring a plurality of heterogeneous processing elements;

wherein the protocol file includes allocation information for the plurality of mesh networks.

3. The method of claim 1 wherein the plurality of mesh networks includes a first plane and a second plane, and allocating comprises dedicating the first plane to control and dedicating the second plane to data.

4. The method of claim 3 further comprising re-allocating the first plane to be shared between data and control.

5. The method of claim 1 wherein the plurality of mesh networks includes a first plane and a second plane, and allocating comprises allocating the first plane to be shared between data and control.

6. The method of claim 1 wherein the plurality of mesh networks includes a first plane and a second plane, and allocating comprises allocating both the first plane and the second plane to be shared between data and control.

7. A method comprising:

translating a design description into a configuration for a plurality of heterogeneous processing elements; and

allocating a plurality of mesh interconnect networks between data and control.

8. The method of claim 7 wherein allocating comprises determining whether latency constraints can be met with a shared data and control mesh network.

9. The method of claim 7 wherein translating and allocating results in a protocol file, the method further comprising storing the protocol file in a memory.

10. The method of claim 9 further comprising translating a second design description and performing a second allocation, resulting in a second protocol file, and storing the second protocol file in the memory.

11. An apparatus including a medium to hold machine-accessible instructions that when accessed result in a machine performing:

allocating a plurality of mesh networks for data and control in a heterogeneous reconfigurable device.

12. The apparatus of claim 11 wherein the plurality of mesh networks includes a first plane and a second plane, and allocating comprises dedicating the first plane to control and dedicating the second plane to data.

13. The apparatus of claim 12 further comprising re-allocating the first plane to be shared between data and control.

14. The apparatus of claim 11 wherein the plurality of mesh networks includes a first plane and a second plane, and allocating comprises allocating the first plane to be shared between data and control.

15. An apparatus comprising:

a heterogeneous network of processing elements; and

first and second mesh networks coupled to the heterogeneous network of processing elements, wherein the apparatus is programmable to utilize the first and second mesh networks for any combination of data and control.

16. The apparatus of claim 15 further comprising a processor to dynamically allocate the first and second mesh networks between data and control.

17. The apparatus of claim 15 wherein the heterogeneous network of processing elements are configurable to communicate over the first and second mesh networks using packets of information.

18. The apparatus of claim 15 wherein the heterogeneous network of processing elements is configurable to utilize the first mesh network for data communication and the second mesh network for control communication.

19. The apparatus of claim 18 wherein the heterogeneous network of processing elements is configurable to utilize the first mesh network for data communication and the second mesh network for both data and control communication.

20. The apparatus of claim 18 wherein the heterogeneous network of processing elements is configurable to utilize both the first and second mesh networks for both data and control communication.

21. An apparatus comprising:

a dual mesh interconnect network; and

a plurality of processing elements coupled to the dual mesh interconnect network, wherein the plurality of processing elements are configurable to utilize the dual mesh interconnect network for any combination of data and control.

22. The apparatus of claim 21 further comprising a processor to configure the plurality of processing elements.

23. The apparatus of claim 21 further comprising a plurality of routers coupled between the dual mesh interconnect network and the plurality of processing elements.

24. The apparatus of claim 21 wherein the dual mesh interconnect network includes a first plane and a second plane, and the plurality of processing elements are configurable to utilize the first plane for data communication and the second plane for control communication.

25. The apparatus of claim 24 wherein the plurality of processing elements are configurable to utilize the first plane for data communication and the second plane for both data and control communication.

26. The apparatus of claim 24 wherein the plurality of processing elements are configurable to utilize both the first and second planes for both data and control communication.

27. An electronic system comprising.

an antenna;

a radio frequency circuit to receive communications signals from the antenna; and

a reconfigurable device coupled to the radio frequency circuit, the reconfigurable device including a dual mesh interconnect network, and a plurality of processing elements coupled to the dual mesh interconnect network, wherein the plurality of processing elements are configurable to utilize the dual mesh interconnect network for any combination of data and control.

28. The electronic system of claim 27 further comprising a processor to configure the plurality of processing elements.

29. The electronic system of claim 27 wherein the dual mesh interconnect network includes a first plane and a second plane, and the plurality of processing elements are configurable to utilize the first plane for data communication and the second plane for control communication.

30. The electronic system of claim 29 wherein the plurality of processing elements are configurable to utilize the first plane for data communication and the second plane for both data and control communication.