Structure and method for fabricating GaN devices utilizing the formation of a compliant substrate

• US 20050194593A1
• Filed: 04/29/2005
• Published: 09/08/2005
• Est. Priority Date: 01/19/2001
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ramdani, Jamal, Hilt, Lyndee L.
• Granted Patent: US 7,211,852 B2
• Time in Patent Office: Days
• US Class Current: 257/52
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/02293 formation of epitaxial layers by a deposition process epitaxial growth per se C30B
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 33/007 comprising nitride compounds

Abstract

High quality epitaxial layers of GaN can be grown overlying large silicon wafers (200) by forming an amorphous layer (210) on the substrate. The amorphous layer dissipates strain and permits the growth of a high quality GaN layer (208). Any lattice mismatch between the GaN layer and the underlying substrate is taken care of by the amorphous layer.

Claims

1-42. -42. (canceled)

43. A semiconductor structure comprising:

a monocrystalline substrate;

an amorphous oxide layer formed on the substrate and comprising at least one material selected from the group consisting of Sr_zBa_1-zTiO₃, Sr_zBa_1-zZrO₃, Sr_zBa_1-zHfO₃, Sr_zBa_1-zSnO₃ and CaTiO₃, where z ranges from 0 to approximately 1; and

a first monocrystalline nitride material layer having a thickness in the range of from about 20 angstroms to about 50 angstroms overlying the amorphous oxide layer and comprising at least one material selected from the group consisting of GaN, GaInN, AlGaN, SiN and AlN.

44. The semiconductor structure of claim 43, wherein the amorophous oxide layer comprises an oxide formed as a monocrystalline oxide and subsequently heat treated to convert the monocrystalline oxide to an amorphous oxide.

45. The semiconductor structure of claim 43, wherein the first monocrystalline nitride material layer is formed by nitridation of a first monocrystalline material layer selected from the group consisting of GaAs, GaInAs, AlGaAs, Si and AlAs.

46. The semiconductor structure of claim 43, wherein the substrate comprises silicon.

47. The semiconductor structure of claim 43, further comprising a monocrystalline material layer formed overlying the amorphous oxide layer and underlying the first monocrystalline nitride material layer.

48. The semiconductor structure of claim 43, further comprising a template layer positioned between the amorphous oxide layer and the monocrystalline nitride material layer.

49. The semiconductor structure of claim 48, wherein the template layer comprises at least one material selected from the group consisting of Ti—

As, Sr—

O—

As, Sr—

Ga—

O, Ti—

O—

As, and Sr—

Al—

O.

50. The semiconductor structure of claim 48, wherein the template layer comprises a Zintl-type phase material.

51. The semiconductor structure of claim 50, wherein the Zintl-type phase material comprises at least one of SrAl₂, SrAl₄ (MgCaYb)Ga₂, (Ca, Sr, Eu, Yb)In₂, BaGe₂As, and SrSn₂As₂.

52. The semiconductor structure of claim 48, wherein the template layer comprises a surfactant material.

53. The semiconductor structure of claim 52, wherein the surfactant material comprises at least one of Al, In, and Ga.

54. The semiconductor structure of claim 52, wherein the template layer further comprises a capping layer.

55. The semiconductor structure of claim 54, wherein the capping layer is formed by exposing the surfactant material to a cap-inducing material.

56. The semiconductor structure of claim 55, wherein the cap-inducing material comprises at least one of As, P, Sb, and N.

57. The semiconductor structure of claim 54, wherein the surfactant comprises Al, and the capping layer comprises Al₂Sr.

58. The semiconductor structure of claim 43, wherein the amorphous oxide layer formed on the substrate comprises Sr_zBa_1-zTiO₃.

59. The semiconductor structure of claim 43, wherein the amorphous oxide layer formed on the substrate comprises Sr_zBa_1-zZrO₃.

60. The semiconductor structure of claim 43, wherein the amorphous oxide layer formed on the substrate comprises Sr_zBa_1-zHfO₃.

61. The semiconductor structure of claim 43, wherein the amorphous oxide layer formed on the substrate comprises Sr_zBa_1-zSnO₃.

62. The semiconductor structure of claim 43, wherein the amorphous oxide layer formed on the substrate comprises CaTiO₃.