Increasing carrier mobility in NFET and PFET transistors on a common wafer

• US 20050194596A1
• Filed: 04/21/2005
• Published: 09/08/2005
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Haining Yang, Victor Chan
• Original Assignee: Haining Yang, Victor Chan
• Inventors: Chan, Victor, Yang, Haining
• Granted Patent: US 7,211,869 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

Claims

1-11. -11. (canceled)

12. An integrated circuit comprising

a first circuit element,

a second circuit element,

a first layer of material overlying said first circuit element and said second circuit element and having a first stress level in a first region of said first layer and a second stress level in a second region of said first layer, and

a second layer of material overlying said first circuit element and said second circuit element and having a first stress level in a first region of said second layer and a second stress level in a second region of said second layer, wherein said second stress level in each of said first and second layers is reduced from the first stress level in each of said first and second layers.

13. The integrated circuit as recited in claim 12,

wherein said first layer and said second layer comprise an etch stop layer.

14. The integrated circuit as recite in claim 12 wherein one of said first layer and said second layer is one of silicon nitride or silicon oxynitride.

15. The integrated circuit as recited in claim 12, wherein said first circuit element is a first transistor and said second circuit element is a second transistor.

16. The integrated circuit as recited in claim 15, wherein said first and second transistors are field effect transistors of complementary conductivity types.

17. The integrated circuit as recited in claim 12, wherein said second region of each of said first and second layers is implanted with a heavy ion.

18. The integrated circuit as recited in claim 17, wherein said heavy ions are of germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon.

19. The integrated circuit as recited in claim 12, wherein said first layer and said second layer are of different thickness.

20. The integrated circuit as recited in claim 12, wherein said first stress levels in each of said first and second layers is in the range of −

2.0 to +2.0 GPa.