Semiconductor device and manufacturing method of the same

• US 20050194670A1
• Filed: 02/10/2005
• Published: 09/08/2005
• Est. Priority Date: 02/17/2004
• Status: Active Grant

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Okayama, Yoshio, Suzuki, Akira, Kameyama, Koujiro
• Granted Patent: US 8,278,213 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

This invention improves reliability of a semiconductor device and a manufacturing method thereof. A glass substrate is bonded on a surface of a silicon wafer formed with pad electrodes. Next, via holes are formed from a back surface of the silicon wafer to pad electrodes, and a groove is formed extending along a center line of a dicing line and penetrating the silicon wafer from its back surface. After then, in processes including heating treatment, cushioning pads, wirings, a solder mask, and solder balls are formed on the back surface of the silicon wafer. Finally, the silicon wafer bolstered by the glass substrate is separated into individual silicon dice by dicing.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a pad electrode formed on a top surface thereof;

bonding a supporting member to the top surface of the semiconductor substrate;

forming a via hole penetrating the semiconductor substrate from a back surface thereof to expose a surface of the pad electrode; and

forming a groove extending along a dicing line and penetrating the semiconductor substrate from the back surface of the semiconductor substrate.

2. The method of claim 1, further comprising heating the semiconductor substrate bonded with the supporting member after forming the groove.

3. The method of claim 1, further comprising:

forming an insulation film over the back surface of the semiconductor substrate so that the insulation film covers inside walls of the via hole and the groove;

etching the insulation film to remove portions of the insulation film at a bottom of the via hole and at the top surface of the semiconductor substrate so that inside-wall insulation films are formed on the inside walls of the via hole and the groove; and

forming a wiring layer that is disposed on the back surface of the semiconductor substrate and connected with the pad electrode through the via hole.

4. The method of claim 3, wherein the wiring layer is formed by plating or by sputtering.

5. The method of claim 3, further comprising forming a protection layer covering the wiring layer and forming a conductive terminal on the wiring layer.

6. A semiconductor device comprising:

a semiconductor die having a via hole;

a pad electrode disposed on a top surface of the semiconductor die so as to cover the via hole;

a supporting member bonded to the top surface of the semiconductor die;

a first insulation film disposed on a sidewall of the via hole;

a second insulation film disposed on an outside sidewall of the semiconductor die; and

a wiring layer disposed on a back surface of the semiconductor die and connected with the pad electrode through the via hole.

7. The semiconductor device of claim 6, wherein the wiring layer comprises a layer formed by plating or by sputtering.

8. The semiconductor device of claim 6, further comprising a protection layer covering the wiring layer and a conductive terminal disposed on the wiring layer.

9. A semiconductor device comprising:

a semiconductor die having a via hole;

a pad electrode disposed on a top surface of the semiconductor die so as to cover the via hole;

a supporting member bonded to the top surface of the semiconductor die; and

a side wall that is formed as a result of dicing and comprises an etched surface of the semiconductor die.