Single and composite binary and multi-valued logic functions from gates and inverters

• US 20050194993A1
• Filed: 11/30/2004
• Published: 09/08/2005
• Est. Priority Date: 02/25/2004
• Status: Active Grant

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Granted Patent: US 7,218,144 B2
• Time in Patent Office: Days
• US Class Current: 326/59
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states. Circuits and methods for implementing ternary and multi-value functions are also disclosed. Corrective design techniques that can be used when a logic expression is incorrectly realized are also disclosed. Circuits that use inverters and gates to realize logic expressions are also provided.

Claims

1. A ternary switch, comprising:

an input,

an output;

and a control input;

wherein the input is connected to the output when the control input is in a first of three states.

2. The ternary switch as claimed in claim 1, wherein the input is disconnected from the output when the control input is in a second or a third of three states.

3. The ternary switch as claimed in claim 2, wherein the input is connected to the output when the control input is a 0.

4. The ternary switch as claimed in claim 2, wherein the input is connected to the output when the control input is a 1.

5. The ternary switch as claimed in claim 2, wherein the input is connected to the output when the control input is a 2.

6. The ternary switch as claimed in claim 1, wherein the input is connected to the output when the control input is in a second of three states.

7. The ternary switch as claimed in claim 6, wherein the input is disconnected from the output when the control input is in a third of three states.

8. A method of switching a signal from an input to an output under the control of a ternary signal, comprising:

conducting the signal on the input to the output when the ternary signal is in a first of three states; and

isolating the signal on the input to the output when the ternary signal is in a second or a third of three states.

9. The ternary switch as claimed in claim 8, wherein the signal is conducted when the ternary signal is a 0.

10. The ternary switch as claimed in claim 8, wherein the signal is conducted when the ternary signal is a 1.

11. The ternary switch as claimed in claim 8, wherein the signal is conducted when the ternary signal is a 2.

12. A method of switching a signal from an input to an output under the control of a ternary signal, comprising:

conducting the signal on the input to the output when the ternary signal is in a first or a second of three states; and

isolating the signal on the input to the output when the ternary signal is in a third of three states.

13. The ternary switch as claimed in claim 12, wherein the signal is conducted when the ternary signal is a 0 or a 1.

14. The ternary switch as claimed in claim 12, wherein the signal is conducted when the ternary signal is a 1 or a 2.

15. The ternary switch as claimed in claim 12, wherein the signal is conducted when the ternary signal is a 0 or a 2.

16. A multi-value switch, comprising:

an input,

an output;

and a control input;

wherein the input is connected to the output when the control input is in a first of x states, x being greater than or equal to four.

17. The multi-value switch as claimed in claim 16, wherein the input is disconnected from the output when the control input is in any state other than the first of x states.

18. The multi-value switch as claimed in claim 17, wherein the input is connected to the output when the control input is a 0.

19. The multi-value switch as claimed in claim 17, wherein the input is connected to the output when the control input is a 1.

20. The multi-value switch as claimed in claim 17, wherein the input is connected to the output when the control input is a 2.

21. The multi-value switch as claimed in claim 17, wherein the input is connected to the output when the control input is a 3.

22. The multi-value switch as claimed in claim 16, wherein the input is connected to the output when the control input is in a second of x states.

23. The multi-value switch as claimed in claim 22, wherein the input is connected to the output when the control input is in a third of x states.

24. A method of switching a signal from an input to an output under the control of a multi-value signal, the multi-value signal being able to assume one of x states wherein x is four or greater, comprising:

conducting the signal on the input to the output when the multi-value signal is in a first of x states; and

isolating the signal on the input to the output when the multi-value signal is not in the first of x states.

25. A method of switching a signal from an input to an output under the control of a multi-value signal, comprising:

conducting the signal on the input to the output when the multi-value signal is in a first or a second of x states; and

isolating the signal on the input to the output when the multi-value signal is not in the first or the second of x states.

26. A method of switching a signal from an input to an output under the control of a multi-value signal, comprising:

conducting the signal on the input to the output when the multi-value signal is in a first or a second or a third of x states; and

isolating the signal on the input to the output when the multi-value signal is not in the first or the second or third of x states.

27. A circuit that expresses a logic equation having three or more variables and two or more logic functions, comprising:

a fixed signal source; and

a series and parallel connection of inverters and switches, the switches enabled by selected ones of the three or more variables in the equation, the series and parallel connection of inverters and switches having an input connected to the fixed signal source and an output.

28. A circuit that solves a logic equation having three or more variables and two or more logic functions, comprising:

an input connected to one of the three or more variables; and

a series and parallel connection of inverters and switches, the switches enabled by selected ones of the three or more variables in the logic equation, the series and parallel connection of inverters and switches having an input connected to the one of the variable signal sources and an output.

29. A circuit for processing a first ternary signal and a second ternary signal in accordance with a ternary logic function, comprising:

a first input that can receive the first ternary signal;

a second input that can receive the second ternary signal;

an output;

a first circuit connected between the first input and the output, the first circuit being enabled when the second ternary signal is in a first of three possible states, the first circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal;

a second circuit connected between the first input and the output, the second circuit being enabled when the second ternary signal is in a second of three possible states, the second circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal;

a third circuit connected between the first input and the output, the third circuit being enabled when the second ternary signal is in a third of three possible states, the third circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal.

30. The circuit as claimed in claim 29, wherein the first circuit, the second circuit and the third circuit each include a combination of inverters and switches.

31. A method of processing a first ternary signal and a second ternary signal in accordance with a ternary logic function in an electronic circuit, comprising:

inputting the first ternary signal and the second ternary signal to a first circuit, a second circuit and a third circuit;

enabling the first circuit when the second ternary signal is in a first of three possible states, the first circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal;

enabling the second circuit when the second ternary signal is in a second of three possible states, the second circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal;

enabling the third circuit when the second ternary signal is in a third of three possible states, the third circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal.

32. The method as claimed in claim 31, wherein the first circuit, the second circuit and the third circuit each include a combination of inverters and switches.

33. A circuit for processing a first multi-value signal and a second multi-value signal in accordance with a multi-value logic function, the first and second multi-value signals being able to assume one of x values wherein x is greater than or equal to four, comprising:

a first input that can receive the first multi-value signal;

a second input that can receive the second multi-value signal;

an output;

x circuits connected between the first input and the output,

the first of the x circuits being enabled when the second multi-value signal is in a first of x possible states, the first circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal;

the second of the x circuits being enabled when the second multi-value signal is in a second of x possible states, the second circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal;

the third of the x circuits being enabled when the second multi-value signal is in a third of x possible states, the third circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal;

the third of the x circuits being enabled when the second multi-value signal is in a third of x possible states, the third circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal;

the xth of x circuits being enabled when the second multi-value signal is in an xth of x possible states, the xth circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal.

34. The circuit as claimed in claim 33, wherein the x circuits each include a combination of inverters and switches.

35. A method of processing a first multi-value signal and a second multi-value signal in accordance with a multi-value logic function in an electronic circuit, comprising:

inputting the first multi-value signal and the second multi-value signal to x circuits;

enabling a first of the x circuits when the second multi-value signal is in a first of x possible states, the first circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal;

enabling a second of the x circuits when the second multi-value signal is in a second of x possible states, the second circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal;

enabling a third of the x circuits when the second multi-value signal is in a third of x possible states, the third circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal;

enabling an xth of the x circuits when the second multi-value signal is in an xth of x possible states, the xth circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal.

36. The method circuit as claimed in claim 35, wherein the x circuits each include a combination of inverters and switches.