Low voltage boosted analog transmission gate
First Claim
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1. A circuit having a pass transistor, comprising:
- a capacitor;
a first inverter and a terminal of the capacitor to receive an enable signal that boosts a charge stored on the capacitor to a voltage potential higher than an operating voltage of the first inverter; and
a second inverter coupled to the first inverter to generate an output signal to drive a gate of the pass transistor, where the second inverter receives power from the voltage potential stored at another terminal of the capacitor.
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Abstract
A drive boost circuit provides a boosted voltage potential for driving the gate of pass device. The drive boost circuit may be one or more stages and include an inverter pair where the first inverter is powered from an operating voltage while the second inverter receives the generated boosted voltage potential that is used to drive the gate of a pass transistor.
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Citations
19 Claims
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1. A circuit having a pass transistor, comprising:
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a capacitor;
a first inverter and a terminal of the capacitor to receive an enable signal that boosts a charge stored on the capacitor to a voltage potential higher than an operating voltage of the first inverter; and
a second inverter coupled to the first inverter to generate an output signal to drive a gate of the pass transistor, where the second inverter receives power from the voltage potential stored at another terminal of the capacitor. - View Dependent Claims (2, 3, 4)
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5. A circuit, comprising:
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a first inverter to receive an enable signal and generate a complemented enable signal, the first inverter to operate from an operating potential and a ground potential; and
a second inverter having an input to receive the complemented enable signal and operate from a boosted voltage potential that is different from the operating potential of the first inverter and supply an output signal having an amplitude greater than an amplitude of the enable signal. - View Dependent Claims (6, 7, 8)
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9. A circuit, comprising:
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a first stage to receive a precharge signal and an enable signal and generate a first boosted signal;
a second stage to receive the precharge signal and the first boosted signal and generate a second boosted signal, where the first and second boosted signals have amplitudes greater than an amplitude of the enable signal; and
a serially connected inverter pair where a first inverter has an input coupled to an output of the second stage and a second inverter receives power from the second boosted signal to generate an output signal. - View Dependent Claims (10, 11, 12)
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13. A system, comprising:
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first and second antennas;
a transceiver coupled to the first and second antennas; and
a processor coupled to the transceiver, wherein the processor includes a first inverter to receive an enable signal and a second inverter to generate an output signal having an amplitude greater than an amplitude of the enable signal. - View Dependent Claims (14, 15, 16)
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17. A method, comprising:
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precharging a node;
transitioning an input signal from a low voltage level to a high voltage level to capacitively couple the node from a first voltage value to a boosted voltage potential;
complementing the input signal in a first inverter; and
using the complemented input signal at a second inverter and the boosted voltage potential to generate an output signal having an amplitude substantially at the boosted voltage potential. - View Dependent Claims (18, 19)
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Specification