Method and apparatus for high rate concurrent read-write applications

• US 20050195203A1
• Filed: 12/14/2004
• Published: 09/08/2005
• Est. Priority Date: 03/02/2004
• Status: Active Grant

• Current Assignee: Ittiam Systems Pte Ltd
• Original Assignee: Ittiam Systems Pte Ltd
• Inventors: Tripathi, Ambudhar, Jain, Mini, Sethuraman, Sriram, Sadanand, Satheesh
• Granted Patent: US 7,511,713 B2
• Time in Patent Office: Days
• US Class Current: 345/536
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate. The second video frame is then read from the second single-ported memory upon completing the writing of the second video frame in the second ported memory. The reading of the second video frame is then repeated from the second single-ported memory to maintain the second frame rate.

Claims

1. An apparatus, comprising:

a source interface module that receives video frames at a first variable frame rate, wherein each video frame has video data;

first and second single-ported memories coupled to the source interface module;

a control logic circuit coupled to the source interface module and the first and second single-ported memories; and

an output interface module coupled to the control logic circuit and the first and second single-ported memories, wherein the control logic circuit controls reading of the video frames from the source interface module and writing of the read video frames to the first and second single-ported memories at the first frame rate, and wherein the first frame rate is lower than the second frame rate,

wherein the control logic circuit controls reading of the video frames from the first and second single-ported memories and writing of the read video frames to the output interface module at a second frame rate, and wherein the first variable frame rate is lower than the second frame rate.

2. The apparatus of claim 1, wherein the control logic circuit controls writing of a current video frame to the output interface module at the second frame rate by repeating the writing of the current video frame by R times, wherein R is a repetition ratio, and wherein R is computed using the equation:

Repetition ratio R=(second frame rate/first frame rate)

3. The apparatus of claim 2, wherein each video frame comprises video data, and wherein video data comprises multiple bytes.

4. The apparatus of claim 3, wherein the source interface module comprises first and second buffer memories capable of storing a predetermined number of words, wherein the control logic circuit controls writing the received video data by the source interface module to the first and second buffer memories such that while writing the predetermined number of words to one of the first and second buffer memories the other of one of the first and second buffer memories is being read by the one of the first and second single-ported memories at the first variable frame rate.

5. The apparatus of claim 1, wherein the output interface module comprises first and second FIFO buffers, wherein upon completion of writing the current video frame in either one of the first and second single-ported memories the written video frame is read into one of the first and second FIFO buffers on a line-by-line basis.

6. The apparatus of claim 1, further comprising a sync generator that generates a Hsync (horizontal synchronization) signal and a Vsync (vertical synchronization) signal, wherein the generated Hsync signal and the Vsync signal define boundaries of a video line and a video frame, respectively.

7. The apparatus of claim 1, further comprising a display device that receives the outputted video frame data along with the Hsync signal and the Vsync signal and displays the video frame data.

8. The apparatus of claim 1, wherein the single-ported memories are selected from the group the comprising of SDRAM (Synchronous Dynamic Random Access Memory) and SRAM (Static Random Access Memory).

9. The apparatus of claim 1, wherein the first frame rate is selected from the group comprising of a first variable frame rate and a first fixed frame rate.

10. A system comprising:

a network interface;

a processing unit coupled to the network interface, wherein the processing unit comprising;

a video decoder to receive a sequence of video frames via the network interface, wherein the video decoder comprises;

a source interface module that receives the sequence of video frames at a first frame rate from the processing unit, wherein each video frame has video data;

first and second single-ported memories coupled to the source interface module;

a control logic circuit coupled to the source interface module and the first and second single-ported memories; and

an output interface module coupled to the control logic circuit and the first and second single-ported memories, wherein the control logic circuit controls reading of the video frames from the source interface module and writing of the read video frames to the first and second single-ported memories at the first frame rate,

wherein the control logic circuit controls reading of the video frames from the first and second single-ported memories and writing of the read video frames to the output interface module at a second frame rate, and wherein the first frame rate is lower than the second frame rate.

11. The system of claim 10, wherein the control logic circuit controls writing of a current video frame to the output interface module at the second frame rate by repeating the writing of the current video frame by R times, wherein R is a repetition ratio, and wherein R is computed using the equation:

Repetition ratio R=(second frame rate/first frame rate)

12. The system of claim 11, wherein the single-ported memories are selected from the group the comprising of SDRAM and SRAM.

13. A method comprising:

receiving a sequence of video frames at a first variable frame rate;

writing a first video frame in a first single-ported memory;

reading the first video frame from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory;

repeating the reading of the first video frame from the first single-ported memory to maintain a second frame rate, wherein the second frame rate is higher than the first variable frame rate;

writing a second video frame in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate;

reading the second video frame from the second single-ported memory upon completing the writing of the second video frame in the second ported memory; and

repeating the reading of the second video frame from the second single-ported memory to maintain the second frame rate.

14. The method of claim 13, further comprising:

repeating the above steps for the subsequent video frames.

15. The method of claim 13, wherein, in writing the current video in the first single-ported memory and writing the next video frame in the second single-ported memory, the single-ported memory comprises memories selected from the group consisting of SDRAMs and SRAMs.

16. A method comprising:

receiving a sequence of video frames at a first frame rate;

writing a first video frame in a first single-ported memory;

reading the first video frame from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory;

repeating the reading of the first video frame from the first single-ported memory to maintain a second frame rate, wherein the second frame rate is higher than the first frame rate;

writing a second video frame in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first frame rate;

reading the second video frame from the second single-ported memory upon completing the writing of the second video frame in the second ported memory; and

repeating the reading of the second video frame from the second single-ported memory to maintain the second frame rate.

17. The method of claim 16, further comprising:

repeating the above steps for the subsequent video frames.

18. The method of claim 17, wherein, in writing the current video in the first single-ported memory and writing the next video frame in the second single-ported memory, the single-ported memory comprises memories selected from the group consisting of SDRAMs and SRAMs.