Semiconductor memory device with a stacked gate including a floating gate and a control gate

• US 20050195636A1
• Filed: 12/21/2004
• Published: 09/08/2005
• Est. Priority Date: 12/22/2003
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Umezawa, Akira, Kakizoe, Kazuhiko
• Granted Patent: US 7,120,057 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells

Abstract

A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS transistor formed on the first semiconductor layer, a second and a third MOS transistor which are formed on the second and third semiconductor layers, respectively, a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors, and a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer. The first wiring layer is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor.

Claims

1. A semiconductor memory device comprising:

a first to a fourth semiconductor layer of a first conductivity type which are formed in a surface region of a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another;

memory cells each of which includes a first MOS transistor of the second conductivity type formed on the first semiconductor layer;

a second and a third MOS transistor of the second conductivity type which are formed on the second and third semiconductor layers, respectively;

a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors and which is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor; and

a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer.

2. The semiconductor memory device according to claim 1, wherein the fourth semiconductor layer has a higher impurity concentration than that of the first to third semiconductor layers.

3. The semiconductor memory device according to claim 1, further comprising:

a second metal wiring layer which is formed in a layer higher than the first metal wiring layer so as to be parallel to the gate of the first MOS transistor and which is connected to the first metal wiring layer by a second contact plug.

4. The semiconductor memory device according to claim 1, wherein each of the memory cells further includes a fourth MOS transistor of the second conductivity type,

the fourth MOS transistor including

a stacked gate which includes a floating gate formed on the first semiconductor layer with a gate insulating film interposed therebetween and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween, and

a source connected to the drain of the first MOS transistor.

5. The semiconductor memory device according to claim 4, further comprising:

a memory cell array in which the memory cells are arranged in a matrix;

bit lines each of which connects commonly the drains of the fourth MOS transistors of the memory cells in a same column;

word lines each of which is formed by connecting commonly the control gates of the fourth MOS transistors of the memory cells in a single row;

select gate lines each of which is formed by connecting commonly the gates of the first MOS transistors of the memory cells in a same row;

a first row decoder which selects any one of the select gate lines in a read operation; and

a second row decoder which selects any one of the word lines in a write operation.

6. The semiconductor memory device according to claim 5, further comprising:

a negative voltage supplying circuit which supplies a negative voltage, wherein

the first row decoder includes;

the first MOS transistors which are provided for the select gate lines in a one-to-one correspondence and which are turned off in a write operation and an erase operation and are turned on in a read operation; and

a first row address decoding circuit which selects any one of the select gate lines in a read operation and supplies a potential to the selected select gate line via the first MOS transistor, and

the second row decoder includes;

the second MOS transistors which are provided for the select gate lines in a one-to-one correspondence and which are turned on in a write operation and are turned off in a read operation and an erase operation; and

a second row address decoding circuit which selects any one of the word lines in a write operation and applies a potential to the selected word line,

the second row decoder supplies the negative voltage supplied from the negative voltage supplying circuit to the select gate line via the second MOS transistor.

7. A semiconductor memory device comprising:

a first to a third semiconductor layer of a first conductivity type which are formed in a surface region of a fourth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another;

memory cells each of which includes a first MOS transistor of the second conductivity type formed on the first semiconductor layer;

a second and a third MOS transistor of the second conductivity type which are formed on the second and third semiconductor layers, respectively;

a fifth semiconductor layer of the second conductivity type formed so as to be isolated from the fourth semiconductor layer;

a sixth semiconductor layer of the first conductivity type formed in a surface region of the fifth semiconductor layer;

a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors and which is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor; and

a second contact plug which connects the sixth semiconductor layer to the first metal wiring layer.

8. The semiconductor memory device according to claim 7, wherein the sixth semiconductor layer has a higher impurity concentration than that of the first to third semiconductor layers.

9. The semiconductor memory device according to claim 7, further comprising:

a second metal wiring layer which is formed in a layer higher than the first metal wiring layer so as to be parallel to the gate of the first MOS transistor and which is connected to the first metal wiring layer by a second contact plug.

10. The semiconductor memory device according to claim 7, wherein each of the memory cells further includes a fourth MOS transistor of the second conductivity type,

the fourth MOS transistor including:

a stacked gate which includes a floating gate formed above the first semiconductor layer with a gate insulating film interposed therebetween and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween; and

a source connected to the drain of the first MOS transistor.

11. The semiconductor memory device according to claim 10, further comprising:

a memory cell array in which the memory cells are arranged in a matrix;

bit lines each of which connects commonly the drains of the fourth MOS transistors of the memory cells in a same column;

word lines each of which is formed by connecting commonly the control gates of the fourth MOS transistors of the memory cells in a same row;

select gate lines each of which is formed by connecting commonly the gates of the first MOS transistors of the memory cells in a same row;

a first row decoder which selects any one of the select gate lines in a read operation; and

a second row decoder which selects any one of the word lines in a write operation.

12. The semiconductor memory device according to claim 11, further comprising:

a negative voltage supplying circuit which supplies a negative voltage, wherein

the first row decoder includes;

the first MOS transistors which are provided for the select gate lines in a one-to-one correspondence and which are turned off in a write operation and an erase operation and are turned on in a read operation; and

a first row address decoding circuit which selects any one of the select gate lines in a read operation and supplies a potential to the selected select gate line via the first MOS transistor, and

the second row decoder includes;

the second MOS transistors which are provided for the select gate lines in a one-to-one correspondence and which are turned on in a write operation and are turned off in a read operation and an erase operation; and

a second row address decoding circuit which selects any one of the word lines in a write operation and applies a potential to the selected word line,

the second row decoder supplies the negative voltage supplied from the negative voltage supplying circuit to the select gate line via the second MOS transistor.