Method and apparatus for crystal drift compensation

• US 20050195917A1
• Filed: 06/30/2004
• Published: 09/08/2005
• Est. Priority Date: 03/05/2004
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leipold, Dirk, Staszewski, Robert B.
• Application Number:
  US10/883,501
• Publication Number:
  US 20050195917A1
• Time in Patent Office: Days
• US Class Current: 375/295
• CPC Class Codes: H03C 3/0941 applying frequency modulation at more than one point in the loop
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03C 3/0966 modulating the reference clock
• CPC Class Codes: H03J 7/047 Automatic frequency control using an auxiliary signal, e.g. low frequency scanning of the locking range or superimposing a special signal on the input signal
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop

Abstract

A mobile device includes frequency synthesizer circuitry for generating a channel frequency at a multiple of a reference frequency. The reference frequency is generated by a free-running crystal oscillator, without frequency stabilization circuitry. Variations in the output of the crystal oscillator are compensated by adjusting the multiplication factor of the frequency synthesizer.

Claims

1. A receiver comprising:

a time base for generating a reference signal having a reference frequency;

a frequency multiplying circuit for generating an output signal having an output frequency responsive to the reference frequency and a digital frequency command word;

circuitry for adjusting the frequency command word responsive to a variation between the output frequency and a predetermined frequency.

2. The receiver of claim 1 wherein the circuitry for adjusting the frequency command word comprises circuitry for adding a predetermined frequency command word to a variable frequency command word.

3. The receiver of claim 2 wherein the receiver is in communication with a base station, and the base station provides data to generate the variable frequency command word.

4. The receiver of claim 2 wherein the receiver is in communication with a base station and receives a base station reference frequency signal and generates the variable frequency command word responsive to a comparison between the output frequency and the base station reference frequency.

5. The receiver of claim 1 wherein the frequency multiplying circuit comprises a phase locked loop circuit.

6. The receiver of claim 1 wherein the time base comprises a crystal oscillator.

7. The receiver of claim 1 wherein the time base further comprises circuitry for controlling the value of the reference frequency, such that the reference frequency can be set to a rough approximation of a desired reference frequency.

8. A transmitter comprising:

a time base for generating a reference signal having a reference frequency;

a frequency multiplying circuit for generating an output signal having an output frequency responsive to the reference frequency and a digital frequency command word;

circuitry for adjusting the frequency command word responsive to a variation between the output frequency and a predetermined frequency.

9. The transmitter of claim 8 and further comprising a pulse-shaping filter for generating data values for modulation on the output signal, wherein said pulse shaping filter is clocked synchronously with the output signal.

10. The transmitter of claim 9 and further comprising a frequency divider circuit for dividing the frequency of the output signal by a predetermined divisor.

11. A method of generating an output signal having a predetermined frequency, comprising the steps of:

generating a reference signal having a reference frequency in a time base;

generating an output signal having an output frequency responsive to the reference frequency and a digital frequency command word;

adjusting the frequency command word responsive to a variation between the output frequency and a predetermined frequency.

12. The method of claim 11 wherein said adjusting step comprises the step of adjusting the frequency command word to compensate for variations between the reference frequency and a specified frequency for the time base.

13. The method of claim 12 wherein the step of generating a reference signal comprises the step of setting the time base to a coarse approximation of a desired frequency.

14. The method of claim 11 wherein the step of adjusting the frequency command word comprises the step of adding a predetermined frequency command word to a variable frequency command word.

15. The method of claim 14 and further comprising the step of receiving data from a base station to generate the variable frequency command word.

16. The method of claim of claim 14 and further comprising the steps of:

receiving a base station reference frequency signal from a base station; and

generating the variable frequency command word responsive to a comparison between the output frequency and the base station reference frequency.

17. The method of claim 11 wherein the step of generating the output signal comprises the step of generating the output frequency in a phase locked loop circuit responsive to the reference frequency and a digital frequency command word.

18. The method of claim 11 and further comprising the steps of:

generating data values for modulation on the output signal in pulse-shaping filter; and

clocking the pulse-shaping filter synchronously with the output signal.

19. A receiver comprising:

a time base for generating a reference signal having a reference frequency;

control circuitry for controlling the reference frequency of the time base responsive to a frequency correction signal;

a digitally controlled frequency synthesizer for generating an output signal with an output frequency at a multiple of the reference frequency;

circuitry for clocking the control circuitry synchronously with edges of the output signal.

20. The receiver of claim 19 wherein the clocking circuitry comprises circuitry for clocking the control circuitry with edges of the reference signal for a first period and clocking the control circuitry synchronously with edges of the output signal for a second period.

21. The receiver of claim 19 wherein said clocking circuitry comprises circuitry for clocking the control circuitry synchronously with edges of the reference signal whenever the output signal is not stable.

22. The receiver of claim 19 wherein said clocking circuitry comprises circuitry for clocking the control circuitry with the reference signal retimed to an edge of the output signal.

23. A transmitter comprising:

a time base for generating a reference signal having a reference frequency;

control circuitry for controlling the reference frequency of the time base responsive to a frequency correction signal;

a frequency synthesizer for generating an output signal with an output frequency at a multiple of the reference frequency;

circuitry for clocking the control circuitry synchronously with edges of the output signal.

24. The transmitter of claim 23 wherein the clocking circuitry comprises circuitry for clocking the control circuitry synchronously with edges of the reference signal for a first period and clocking the control circuitry synchronously with edges of the output signal for a second period.

25. The transmitter of claim 23 wherein said clocking circuitry comprises circuitry for clocking the control circuitry synchronously with edges of the reference signal whenever the output signal is not stable.

26. The transmitter of claim 23 wherein said clocking circuitry comprises circuitry for clocking the control circuitry with the reference signal retimed to an edge of the output signal.

27. A method of generating an output signal having a predetermined frequency, comprising the steps of

generating a reference signal having a reference frequency in a time base;

controlling the reference frequency of the time base with a control circuit responsive to a frequency correction signal;

generating an output signal with an output frequency at a multiple of the reference frequency in a frequency synthesizer;

clocking the control circuit synchronously with edges of the output signal.

28. The method of claim 27 wherein the clocking step comprises the step of clocking the control circuit synchronously with edges of the reference signal for a first period and clocking the control circuit synchronously with edges of the output signal for a-second period.

29. The method of claim 27 wherein said clocking step comprises the step of clocking the control circuit synchronously with edges of the reference signal whenever the output signal is not stable.

30. The method of claim 27 wherein said clocking step comprises the step of clocking the control circuit with the reference signal retimed to an edge of the output signal.

31. A phase locked loop circuit comprising:

circuitry for generating an output signal at a frequency multiple of a reference signal, responsive in part to variable phase information associated with a difference between edges of the reference signal and edges of the output signal;

circuitry for sampling the reference signal on both rising and falling edges of the output signal to produce first and second retimed reference signals;

circuitry for selecting from either the first or second retimed reference signal responsive to a metastability control signal;

circuitry for sampling low-order variable phase information on both the first and second retimed reference signals to produce first and second variable phase samples;

circuitry for selecting from either the first or second variable phase samples responsive to a metastability control signal;

circuitry for sampling higher-order variable phase information responsive to the selected retimed reference signal.

32. The phase locked loop circuit of claim 31 wherein said higher order variable phase information is generated by incrementing a value responsive to a most significant bit of the low-order variable phase information.

33. A method of generating an output signal as a frequency multiple of a reference signal, responsive in part to variable phase information associated with a difference between edges of the reference signal and edges of the output signal, comprising the steps of:

sampling the reference signal on both rising and falling edges of the output signal to produce first and second retimed reference signals;

selecting from either the first or second retimed reference signal responsive to a metastability control signal;

sampling low-order variable phase information on both first and second retimed reference signals to produce first and second variable phase samples;

selecting from either the first or second variable phase samples responsive to a metastability control signal;

sampling higher-order variable phase information responsive to the selected retimed reference signal.

34. The method of claim 33 wherein said higher order variable phase information is generated by incrementing a value responsive to a most significant bit of the low-order variable phase information.