Determination of memory configuration

• US 20050198449A1
• Filed: 03/05/2004
• Published: 09/08/2005
• Est. Priority Date: 03/05/2004
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Haskell, Darrell, Vu, Paul
• Application Number:
  US10/794,147
• Publication Number:
  US 20050198449A1
• Time in Patent Office: Days
• US Class Current: 711/156
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A system is disclosed that comprises a processor, a memory subsystem coupled to the processor, a display coupled to the processor, and logic accessible to the processor that determines the configuration of the memory subsystem and provides a graphical image indicating the memory subsystem'"'"'s configuration on the display.

Claims

1. A computer system, comprising:

a processor;

a memory subsystem coupled to said processor;

a display coupled to the processor; and

logic accessible to the processor that determines the configuration of the memory subsystem and provides a graphical image indicating the memory subsystem'"'"'s configuration on the display.

2. The computer system of claim 1 wherein, if said memory subsystem is not configured correctly, said logic provides information on the graphical image that indicates how the memory subsystem is not configured correctly.

3. The computer system of claim 1 wherein said memory subsystem comprises a plurality of cartridges, each cartridge configured to accommodate a plurality of memory devices, and the graphical image includes a representation of each cartridge and the memory devices contained in each cartridge.

4. The computer system of claim 3 wherein the representation of each cartridge and the memory devices includes textual information regarding each memory module.

5. The computer system of claim 4 wherein said textual information includes one or more items of information selected from the group consisting of capacity and bus speed.

6. The computer system of claim 1 wherein said logic comprises executable code.

7. The computer system of claim 1 wherein said memory subsystem comprises a plurality of hot pluggable memory devices and said logic automatically updates said graphical image as a memory device is removed from or added to the memory subsystem.

8. The computer system of claim 1 wherein the memory subsystem can accommodate one or more memory cartridges, each cartridge adapted to receive one or more memory devices, and the graphical image indicates the presence or absence of each of the one more memory cartridges.

9. The computer system of claim 1 wherein the memory subsystem comprises at least one cartridge that can accommodate one or more memory devices and the graphical image indicates the presence or absence of each of the one or more memory devices.

10. The computer system of claim 1 wherein the memory subsystem can be configured for redundant operation and the graphical image indicates whether the memory subsystem is configured for redundant operation.

11. The computer system of claim 1 wherein the memory subsystem is configurable to include a plurality of cartridges, each cartridge contains sockets for a plurality of memory devices and the graphical image indicates status information for each socket or memory device contained in a socket.

12. The computer system of claim 11 wherein the status information indicates whether different types of memory devices are installed in said cartridges.

13. A storage medium on which code is stored, said code being executable by a processor and, when executed by the processor, causes the processor to:

determine a configuration of a plurality of memory modules;

determine whether the configuration satisfies full system operation; and

show a graphical representation of the configuration on a display.

14. The storage medium of claim 13 said code further causing the processor to show the graphical representation if the configuration does not satisfy full system operation.

15. The storage medium of claim 13 wherein said memory modules can be removed and inserted while the system is operational and said code further causes the processor to determine whether the configuration satisfies full system operation and to show an updated graphical representation when a memory module is removed from or inserted into the system.

16. The storage medium of claim 13 wherein said code is executed if the memory modules are configured to permit the code to be executed and the graphical representation to be shown on the display.

17. The storage medium of claim 13 wherein the code further causes the processor to show the graphical representation as indicating the presence or absence of each of the plurality of memory modules.

18. The storage medium of claim 13 wherein the memory modules can be configured for redundant operation and the code further causes the processor to show the graphical image as indicating whether the memory modules are configured for redundant operation.

19. The storage medium of claim 13 wherein the code further causes the processor to show the graphical representation as indicating memory type associated with each module.

20. A method usable in conjunction with a memory subsystem having a plurality of locations in which memory devices may be installed, the method comprising:

initiating a request for information from each of the memory device locations;

if no information is returned from a particular location, determining that no memory device is present in that location;

determining a configuration of the memory subsystem based on any information returned from any memory devices present in the subsystem and based on the determination as to which locations do not have a memory device; and

displaying an image of the configuration.

21. The method of claim 20 wherein the information comprises serial presence detect information stored in non-volatile storage in the memory devices and specifies one or more parameters selected from the group of parameters consisting of memory capacity and bus speed.

22. The method of claim 20 further including determining whether memory devices are inserted in correct locations.

23. The method of claim 22 further including displaying textual data associated with one or more memory devices not being inserted in correct locations.

24. The method of claim 20 further including determining whether a memory device is missing and displaying graphical and textual information indicative of a missing device.

25. A system, comprising:

a processor;

a memory subsystem coupled to said processor and adapted to accommodate a plurality of memory modules;

a display coupled to the processor; and

a means for determining whether the memory modules are installed in the memory subsystem so as to enable full system operation and for graphically displaying an image indicative of the memory modules installed in said memory subsystem.

26. The system of claim 25 wherein said means includes a means for displaying textual information regarding the memory subsystem if the memory modules are not installed so as to enable full system operation, said textual information indicating how the memory modules are not installed to enable full system operation.

27. The system of claim 25 wherein said means includes means for updating said image each time a memory module is removed from or installed in the memory subsystem.