Parallel multithread processor (PMT) with split contexts

• US 20050198476A1
• Filed: 11/12/2004
• Published: 09/08/2005
• Est. Priority Date: 11/14/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Gazsi, Lajos, Lin, Jinan, Nie, Xiaoning, Mehrgardt, Soenke
• Granted Patent: US 7,526,636 B2
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).

Claims

1-33. -33. (canceled)

34. A multithread processor having:

(a) a plurality of M parallel-connected standard processor root units operable to execute program instructions for different threads;

(b) a plurality of N sets of context data in memory, each containing information regarding a current processor state of a corresponding thread; and

(c) a thread monitoring unit operable to selectively cause operable connection of each of the M parallel-connected standard processor root units to a corresponding set of context data.

35. The multithread processor according claim 34 wherein each of the plurality of N sets of context data is stored in a corresponding one of N context memories.

36. The multithread processor according to claim 34, wherein each standard processor root unit includes an instruction decoding/operand fetch unit configured to decode a program instruction and to fetch operands which are addressed within the program instruction.

37. The multithread processor according to claim 34, wherein each standard processor root unit includes an instruction execution unit configured to execute a decoded program instruction.

38. The multithread processor according to claim 37, wherein each standard processor root unit includes a write-back unit configured to write back operation results of the executed decoded program instruction.

39. The multithread processor according to claim 34, wherein each standard processor root unit includes an associated processor monitoring unit.

40. The multithread processor according to claim 35, wherein each context memory includes a register configured to store a program counter, a register bank configured to store operands, and a status register configured to store at least one status flag.

41. The multithread processor according to claim 34, wherein M is less than or equal to N.

42. The multithread processor according to claim 34, further comprising N instruction buffer stores which can be addressed by the thread monitoring unit, and wherein each of the N instruction buffer stores may be operably selectively connected to each standard processor root unit.

43. The multithread processor according to claim 42, wherein the each of the instruction buffer stores is configured to be selectively connected to one or more instruction memories under the control of the thread monitoring unit, the selectively connected instruction buffer store configured to read program instructions addressed by a program counter of one of the N sets of context data.

44. The multithread processor according to claim 42, wherein up to M instruction buffer stores may be operably selectively connected to the M standard processor root processors at the same time.

45. The multithread processor according to claim 34, wherein each of the standard processor root units are operably coupled to provide processed data to a data bus.

46. The multithread processor according to claim 34, wherein each standard processor root unit is operable to process program instructions received under the control of the thread monitoring unit sequentially using a pipeline method.

47. The multithread processor according to claim 34, wherein the plurality of M parallel-connected standard processor root units are substantially identical.

48. The multithread processor according to claim 46, wherein each standard processor root unit is operable to process each program instruction except at least some data access instructions within a predetermined number of clock cycles.

49. The multithread processor according to claim 43, wherein the number of instruction buffer stores corresponds to the number of sets of context data, each instruction buffer store corresponding to a thread.

50. The multithread processor according to claim 34, wherein the thread monitoring unit is further operable to:

receive event control signals,

temporarily store information based on the event control signals, and

produces multiplexer control signals on the output side based on the information.

51. The multithread processor according to claim 50, wherein the event control signals include event control signals generated internal to the multithread processor and event control signals generated external to the multithread processor.

52. The multithread processor according to claim 51, wherein the standard processor root units are further operable to generate the internally-generated event control signals.

53. The multithread processor according to claim 34, wherein at least one of the plurality of standard processor root units comprises a part of a group consisting of a digital signal processor, a protocol processor and a universal processor.

54. The multithread processor according to claim 36, wherein the instruction execution unit of at least one of the plurality of standard processor root units includes at least one of a group consisting of an arithmetic/logic unit (ALU) and an address generator unit (AGU).

55. The multithread processor according to claim 36, further comprising an instruction fetch unit, the instruction fetch unit comprising a first multiplexer, N instruction buffers coupled to the multiplexer, and a second multiplexer coupled to the N instruction buffers.

56. The multithread processor according to claim 36, wherein the instruction decoding/operand fetch unit is operable to decode the program instruction and is further operable to fetch addressed operands from the plurality of N sets of context data in memory.

57. The multithread processor according to claim 34, wherein the thread monitoring unit includes a switching network.

58. The multithread processor according to claim 57, wherein the switching network includes at least one thread number buffer configured to store a queue of thread values, each of the thread values including a thread number.

59. The multithread processor according to claim 57, wherein the switching network includes at least one buffer, each buffer configured to store a value that references a standard processor root unit which is available for processing program instructions and is not processing any program instructions in the current clock cycle.

60. The multithread processor according to claim 58, wherein the switching network includes at least one buffer, each buffer configured to store a value that references standard processor root unit which is available for processing program instructions and is not processing any program instructions in the current clock cycle.

61. The multithread processor according to claim 59, wherein the at least one buffer comprises a (first in/first out) FIFO memory.

62. The multithread processor according to claim 60, wherein the switching network is further operable to store each of the thread values in the thread number buffer store responsive to event control signals.

63. The multithread processor according to claims 62, wherein the switching network is further operable to store each of the standard root processor numbers in the at least one buffer responsive to event control signals.

64. The multithread processor according to claim 59, wherein the at least one buffer comprises a plurality of buffers, and wherein at most M standard processor root numbers are fetched from the plurality of buffers.

65. The multithread processor according to claim 60, wherein the thread monitoring unit is operable to generate a multiplexer control signal based on one of the thread values obtained from the thread number buffer store and one of the standard processor root numbers obtained from the at least one buffer, and wherein the thread monitoring unit is operable to provide the multiplexer control signal to at least a first multiplexer coupled between the sets of context data and the standard root processor unit.