Automatic alignment of integrated circuit and design layout of integrated circuit to more accurately assess the impact of anomalies
First Claim
1. A method for assessing the impact of anomalies comprising the steps of:
- retrieving an image of a physical device;
obtaining a design layout of said image; and
registering said image of said physical device and said design layout of said image in a common frame of reference, wherein said step of registering said image of said physical device and said design layout of said image in said common frame of reference comprises the steps of;
vectorizing said image of said physical device into closed polygons;
matching polygons in said image with polygons in said design layout; and
aligning said image with said design layout of said image using said matched polygons.
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Accused Products
Abstract
A method, computer program product and system for assessing the impact of anomalies in a physical device. An anomaly may be detected in an integrated circuit. Upon detecting an anomaly, an image of the anomaly may be captured. A design layout of the image may be obtained. The image coordinates of the detected anomaly may be transformed into a common reference system, such as the design layout. By using a common unit of reference instead of different reference systems, automatic coordination of the integrated circuit and the design layout may have to be performed once instead of multiple times for multiple tools. The image coordinates of the detected anomaly may be transformed to the coordinates of a common reference system by vectorizing the image, matching polygons in both the image and the design layout and aligning the image of the anomaly with the design layout of the image.
80 Citations
69 Claims
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1. A method for assessing the impact of anomalies comprising the steps of:
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retrieving an image of a physical device;
obtaining a design layout of said image; and
registering said image of said physical device and said design layout of said image in a common frame of reference, wherein said step of registering said image of said physical device and said design layout of said image in said common frame of reference comprises the steps of;
vectorizing said image of said physical device into closed polygons;
matching polygons in said image with polygons in said design layout; and
aligning said image with said design layout of said image using said matched polygons. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A computer program product embodied in a machine readable medium for assessing the impact of anomalies comprising the programming steps of:
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retrieving an image of a physical device;
obtaining a design layout of said image; and
registering said image of said physical device and said design layout of said image in a common frame of reference, wherein said programming step of registering said image of said physical device and said design layout of said image in said common frame of reference comprises the programming steps of;
vectorizing said image of said physical device into closed polygons;
matching polygons in said image with polygons in said design layout; and
aligning said image with said design layout of said image using said matched polygons. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. A system, comprising:
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a memory unit operable for storing a computer program for assessing the impact of anomalies; and
a processor coupled to said memory unit, wherein said processor, responsive to said computer program, comprises;
circuitry for retrieving an image of a physical device;
circuitry for obtaining a design layout of said image; and
circuitry for registering said image of said physical device and said design layout of said image in a common frame of reference, wherein said circuitry for registering said image of said physical device and said design layout of said image in said common frame of reference comprises;
circuitry for vectorizing said image of said physical device into closed polygons;
circuitry for matching polygons in said image with polygons in said design layout; and
circuitry for aligning said image with said design layout of said image using said matched polygons. - View Dependent Claims (48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69)
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Specification