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Automatic alignment of integrated circuit and design layout of integrated circuit to more accurately assess the impact of anomalies

  • US 20050198602A1
  • Filed: 03/05/2004
  • Published: 09/08/2005
  • Est. Priority Date: 03/05/2004
  • Status: Active Grant
First Claim
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1. A method for assessing the impact of anomalies comprising the steps of:

  • retrieving an image of a physical device;

    obtaining a design layout of said image; and

    registering said image of said physical device and said design layout of said image in a common frame of reference, wherein said step of registering said image of said physical device and said design layout of said image in said common frame of reference comprises the steps of;

    vectorizing said image of said physical device into closed polygons;

    matching polygons in said image with polygons in said design layout; and

    aligning said image with said design layout of said image using said matched polygons.

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