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Semiconductor electrochemical etching processes employing closed loop control

  • US 20050199511A1
  • Filed: 01/21/2005
  • Published: 09/15/2005
  • Est. Priority Date: 01/21/2004
  • Status: Active Grant
First Claim
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1. A method of providing closed-loop control over an electrochemical etching process during porous semiconductor fabrication comprising:

  • providing a substrate wafer of single-crystal semiconductor having a first surface and a second surface, disposing the substrate wafer in an electrochemical etching apparatus comprising the semiconductor wafer as an anode, electrolyte, and counter electrode as a cathode, executing an electrochemical etching process wherein at least part of said first surface of the semiconductor wafer is exposed to electrolyte, setting the electrochemical etching parameters to the electrochemical etching system comprising the substrate wafer, electrolyte and counter electrode, and performing the electrochemical etching process at over a process time period, measuring the value of the resistance of the electrochemical etching system at least once during the electrochemical process time period, and adjusting the electrochemical etching parameters according to the measurements of the resistivity of the electrochemical etching system at least once during the electrochemical process time period.

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