Termination structure for trench DMOS device and method of making the same

• US 20050199952A1
• Filed: 02/11/2005
• Published: 09/15/2005
• Est. Priority Date: 05/06/2003
• Status: Active Grant

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chuang, Chiao-Shun, Hsieh, Hsin-Huang, Tseng, Mao-Song, Chang, Su-Wen
• Granted Patent: US 6,998,315 B2
• Time in Patent Office: Days
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.

Claims

1. (canceled)

2. (canceled)

3. (canceled)

4. (canceled)

5. (canceled)

6. (canceled)

7. (canceled)

8. (canceled)

9. (canceled)

10. (canceled)

11. (canceled)

12. (canceled)

13. A method of simultaneously forming a trench DMOS device and a termination structure provided therefor, comprising:

forming an epitaxial layer of a first type conductivity on a substrate of said first type conductivity, said epitaxial layer having a greater doping concentration than said substrate;

forming a body region of a second type conductivity within said epitaxial layer;

forming a plurality of first type trenches and a second type trench through said body region, said second type trench having a greater width than said first type trenches;

growing a gate oxide layer for covering said body region and lining said first type trenches and said second type trench;

filling said first type trenches with gate electrode;

forming a plurality of doped regions of said first type conductivity within said body region between said first type trenches;

forming a passivation layer on said gate oxide layer and covering said gate electrode;

forming a plurality of contact holes between said first type trenches;

forming a plurality of contact regions of a second type conductivity within exposed portions of said body region in said first type trenches;

forming a metal layer on said passivation layer and filling said contact holes and said second type trench; and

forming an opening through said metal layer to expose a part of said passivation layer over a bottom surface of said second type trench, and portions of said passivation layer on side walls of said second type trench being covered by said metal layer.

14. The method of claim 13, wherein said first conductivity is N-type conductivity and said second type conductivity is P-type conductivity.

15. The method of claim 13, wherein said first conductivity is P-type conductivity and said second type conductivity is N-type conductivity.

16. The method of claim 13, wherein said body region has a depth of 1.2 to 2.0 microns.

17. The method of claim 13, wherein said contact holes has a depth of 0.12 to 0.3 micron.

18. The method of claim 13, wherein said first type trenches have a width of 0.3 to 1.0 micron and said second type trench has a width of 5 to 60 microns.

19. The method of claim 13, wherein forming the plurality of contact holes between said first type trenches comprises:

forming a first photoresist layer on said passivation layer;

patterning said first photoresist layer by performing a first photolithography process; and

etching said passivation layer, said gate oxide layer and said body region in turn through apertures in said first photoresist layer to form the plurality of contact holes between said first type trenches.

20. The method of claim 13, wherein forming the opening through said metal layer comprises:

forming a second photoresist layer on said metal layer;

patterning said second photoresist layer by performing a second photolithography process; and

etching said metal layer through apertures in said second photoresist layer to form the opening to expose a part of said passivation layer over the bottom surface of said second type trench, and portions of said passivation layer on side walls of said second type trench being completely covered by said metal layer.

21. The method of claim 13, wherein said plurality of first type trenches and said second type trench are formed simultaneously.

22. The method of claim 13, wherein said gate electrode comprises polysilicon.

23. The method of claim 13, wherein said plurality of doped regions of said first type conductivity are formed by an implantation procedure.

24. (canceled)

25. (canceled)

26. (canceled)