Dimmer control system with memory

• US 20050200317A1
• Filed: 04/25/2005
• Published: 09/15/2005
• Est. Priority Date: 04/18/2003
• Status: Active Grant

• Current Assignee: Eaton Intelligent Power Limited (Eaton Corporation PLC.)
• Original Assignee: Cooper Wiring Devices Incorporated (Eaton Corporation PLC.)
• Inventors: Novikov, Lenny M.
• Granted Patent: US 6,980,122 B2
• Time in Patent Office: Days
• US Class Current: 315/312
• CPC Class Codes: H05B 39/086 with possibility of remote control

Abstract

A dimmer control system has a communication control loop that connects a master unit in series with a plurality of remote units, and it is superimposed in series on the dimmer load line so as to allow two-way communication between the master unit and remote units without affecting the operation of the load. Communications from the master to the remote units are encoded in loop current fluctuations, whereas communications from any remote to the master unit are encoded in loop voltage fluctuations. The master unit has a switched power supply, for use during normal LOAD ON operation, in tandem with a capacitive power supply, for use during LOAD OFF operation of the control units so as to minimize hum. The master unit power supply circuit provides an output rail voltage comprised of a reference voltage for the load superimposed with a control loop voltage for the voltage drop across the series-connected remote units. The master unit has a POWER OFF detection circuit and a non-volatile memory for storing system status information, so that when power is restored, the system can be restored to its former power level. The switch units are formed with a cover frame mounting a switch plate on a hinge axis allowing ON/OFF movement of an opposing side thereof. An array of LED light pipes is mounted in the switch plate aligned with the hinge axis, in order to minimize displacement of the light pipes during actuator movement.

Claims

1-17. -17. (canceled)

18. A dimmer control system for controlling power supplied to a load comprising:

(a) a master unit connected in a communication control loop in series with one or more remote units, wherein said master and remote units each have a power level display for displaying a current power level supplied by the system to the load, and control unit circuitry to allow two-way communication between the master unit and the remote units of the power level to be supplied to the load;

(b) a dimmer load line supplying power to the load, wherein said communication control loop is superimposed in series on the dimmer load line;

(c) said master unit circuitry including a phase-regulated AC switch which is switched on by a switching signal timed at a given time delay from the start of each half-cycle of an AC power line input in order to supply power to the load at a power level determined by the given time delay, wherein said time delay corresponds to the power level indicated by user input to the master or remote units to be supplied to the load; and

(d) said master unit circuitry including an associated non-volatile memory and circuitry for detecting when the AC power line input has been interrupted representing a POWER OFF condition, and for immediately initiating a procedure for writing in the non-volatile memory information representing the status of the system prior to the power interruption, including the power level in effect prior to the power interruption, said system status information being retrieved from the non-volatile memory upon restoration of a POWER ON condition and being used to set the power level to be supplied to the load in accordance with the power level in effect prior to the power interruption.

19. A dimmer control system according to claim 18, wherein the time delay for the load'"'"'s current power level is identified as a 16-bit binary number by a microprocessor of the master unit circuitry and is regularly stored in the microprocessor'"'"'s RAM, and the binary number is retrieved from RAM and written to the non-volatile memory only when a POWER OFF condition is detected.

20. A dimmer control system according to claim 19, wherein the microprocessor remains powered at the onset of a POWER OFF condition by a reservoir capacitor that charges during normal operation, and when power is interrupted, the reservoir capacitor supplies enough power to enable the microprocessor to store the last binary number from RAM into its non-volatile memory.

21. A dimmer control system according to claim 18, further comprising a switched power supply provided in tandem with a capacitive power supply, such that the switched power supply provides power to the master unit circuitry during LOAD ON conditions in order to avoid heat generation that would be incurred by otherwise using the capacitive power supply, and the capacitive power supply is used during LOAD OFF conditions in order to avoid acoustic noise (hum) in the load.

22. A dimmer control system according to claim 18, wherein said communication control loop has a first encoding circuit for encoding communication messages by a first encoding method for transmission from the master unit to be decoded by the remote units in order to update the power level displays of the remote units for the current power level supplied by the system to the load, and a second encoding circuit for encoding communication messages by a second encoding method different from the first encoding method for transmission from any remote unit to be decoded by the master unit in order to set the power level supplied by the system to the load in accordance with user input entered on any of the remote units.

23. A dimmer control system according to claim 22, wherein one encoding circuit encodes the communication messages in loop voltage fluctuations, and the other encoding circuit encodes the communication messages in loop current fluctuations.

24. A dimmer control system according to claim 18, wherein said master unit has a power supply circuit that provides an output rail voltage equal to the sum of a fixed reference voltage and a control loop voltage equivalent to the total voltage drop across the series-connected remote units.

25. A dimmer control system according to claim 18, wherein the power supply circuit of the master unit includes a current source that generates a DC current that flows through the remote units for operation of the remote units, and the total voltage drop across all the remote units in the communication control loop is sensed by the power supply circuit of the master unit and the DC rail voltage is self-adjusted by the power supply circuit accordingly.

26. A dimmer control system according to claim 25, wherein the self-adjustment by the power supply circuit of the master unit is performed by a transistor node connected in a voltage follower arrangement.

27. A dimmer control system according to claim 22, wherein the master unit circuitry has a current source which supplies control loop current which passes through all the remote units in series on the communication control loop, and the master unit causes current fluctuations in said current source current so as to encode communication messages in loop current fluctuations.

28. A dimmer control system according to claim 27, wherein said remote units each have a control circuit with a resistor which detects the loop current fluctuations as voltage changes across said resistor and decodes them as logical highs and lows of a corresponding digital message.

29. A dimmer control system according to claim 22, wherein the control unit circuitry of each of the remote units has a switch that changes a voltage drop across the remote units and causes voltage fluctuations in the control loop so as to encode communication messages in loop voltage fluctuations.

30. A dimmer control system according to claim 29, wherein the loop voltage fluctuations generated by a remote unit are passed to the master unit which detects the loop voltage fluctuations and decodes them as logical highs and lows of a corresponding digital message.

31. A dimmer control system according to claim 22, wherein the communication control loop is hosted and synchronized by the master unit, and communication messages are transmitted by the master unit close to the start of each positive half cycle of input line voltage in order to minimize the effects of noise.

32. A dimmer control system according to claim 31, wherein the communication messages are transmitted by any of the remote units close to a start of each negative half cycle of input line voltage, and the master unit uses time gating of the communication messages in order to minimize the effects of noise.

33. A dimmer control system according to claim 22, wherein the communication control loop is hosted and synchronized by the master unit, and communication messages are transmitted by the master unit close to the start of each negative half cycle of input line voltage in order to minimize the effects of noise.

34. A dimmer control system according to claim 33, wherein the communication messages are transmitted by any of the remote units close to a start of each positive half cycle of input line voltage, and the master unit uses time gating of the communication messages in order to minimize the effects of noise.

35. A dimmer control system according to claim 18, wherein said master unit has a power supply circuit that provides an output rail voltage equal to the sum of a total control loop voltage drop and a fixed reference voltage.

36. A dimmer control device for controlling power supplied to a load comprising:

(a) a phase-regulated AC switch which is switched on by a switching signal timed at a given time delay from the start of each half-cycle of an AC power line input in order to supply power to the load at a power level determined by the given time delay, wherein said time delay corresponds to the power level indicated by user input to the device to be supplied to the load; and

(b) an associated non-volatile memory and circuitry for detecting when the AC power line input has been interrupted representing a POWER OFF condition, and for immediately initiating a procedure for writing in the non-volatile memory information representing the status of the system prior to the power interruption, including the power level in effect prior to the power interruption, said system status information being retrieved from the non-volatile memory upon restoration of a POWER ON condition and being used to set the power level to be supplied to the load in accordance with the power level in effect prior to the power interruption.

37. A dimmer control device according to claim 36, wherein the time delay for the load'"'"'s current power level is identified as a 16-bit binary number by a microprocessor and is regularly stored in the microprocessor'"'"'s RAM, and the binary number is retrieved from RAM and written to the non-volatile memory only when a POWER OFF condition is detected.

38. A dimmer control device according to claim 37, wherein the microprocessor remains powered at the onset of a POWER OFF condition by a reservoir capacitor that charges during normal operation, and when power is interrupted, the reservoir capacitor supplies enough power to enable the microprocessor to store the last binary number from RAM into its non-volatile memory.

39. A dimmer control device according to claim 36, further comprising a switched power supply provided in tandem with a capacitive power supply, such that the switched power supply provides power to the device during LOAD ON conditions in order to avoid heat generation that would be incurred by otherwise using the capacitive power supply, and the capacitive power supply is used during LOAD OFF conditions in order to avoid acoustic noise (hum) in the load.