Semiconductor output circuit

• US 20050201027A1
• Filed: 03/15/2005
• Published: 09/15/2005
• Est. Priority Date: 03/15/2004
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Takahashi, Shigeki, Arashima, Yoshinori, Abe, Hirofumi
• Granted Patent: US 7,183,802 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches

Abstract

The semiconductor output circuit of the invention has an insulated gate transistor including a first terminal, a second terminal and a gate terminal, a conductive state of the insulated gate transistor being controlled by a drive circuit connected to the gate terminal, a capacitive element and a first resistor connected in series between the second terminal and the gate terminal, and a second resistor connected between the gate terminal and the first terminal. The insulated gate transistor has a cell area formed on a semiconductor substrate, in which a plurality of unit cells each defining a unit transistor connected between the first and second terminals are laid out. The second resistor has such a resistance that all of the unit transistors defined by the unit cells are turned on uniformly when electrostatic discharge is applied to the first or second terminal.

Claims

1. A semiconductor output circuit comprising:

an insulated gate transistor including a first terminal, a second terminal and a gate terminal, a conductive state of said insulated gate transistor being controlled by a drive circuit connected to said gate terminal;

a capacitive element and a first resistor connected in series between said second terminal and said gate terminal;

a second resistor connected between said gate terminal and said first terminal;

said insulated gate transistor having a cell area formed on a semiconductor substrate, in which a plurality of unit cells each defining a unit transistor connected between said first and second terminals are laid out,

said second resistor having such a resistance that all of unit transistors defined by said unit cells are turned on uniformly when electrostatic discharge is applied to said first or second terminal.

2. A semiconductor output circuit according to claim 1, wherein said first and second resistors are connected in series between said gate terminal and said first terminal, and said drive circuit is connected to said gate terminal of said insulated gate transistor through said first resistor.

3. A semiconductor output circuit according to claim 1, wherein said capacitive element is a bipolar transistor.

4. A semiconductor output circuit according to claim 3, wherein a base and an emitter of said bipolar transistor are directly connected with each other.

5. A semiconductor output circuit according to claim 3, wherein a base and an emitter of said bipolar transistor are connected with each other through a third resistor.

6. A semiconductor output circuit according to claim 3, wherein a back-flow preventing diode is connected in series to said bipolar transistor.

7. A semiconductor output circuit according to claim 1, in which said insulated gate transistor is an LDMOS transistor.