Method and apparatus for semiconductor device and semiconductor memory device

• US 20050201150A1
• Filed: 02/09/2005
• Published: 09/15/2005
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Wang, Chih-Hsin
• Granted Patent: US 7,297,634 B2
• Time in Patent Office: Days
• US Class Current: 365/185.300
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a third conductive region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting of charge carriers of one polarity type from the first conductive region, through the filter, and through the second conductive region to the third conductive region while blocking the transport of charge carriers of an opposite polarity from the second conductive region to the first conductive region. The present invention further provides an energy band engineering method permitting the devices be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Claims

1. A semiconductor device, comprising:

a first conductive region;

a second conductive region disposed adjacent to and insulated from the first conductive region;

a third conductive region disposed adjacent to and insulated from the second conductive region; and

a strain source providing a mechanical stress to at least one of the first and the second conductive regions.

2. The device of claim 1, further comprising:

a charge injection filter disposed in between the first and the second conductive regions, wherein the charge injection filter permits transporting of charge carriers of one polarity type from the first conductive region through the second conductive region to the third conductive region and blocks transporting of charge carriers of an opposite polarity type from the second conductive region to the first conductive region.

3. The device of claim 1, wherein the mechanical stress is a tensile stress.

4. The device of claim 1, wherein the mechanical stress is a compressive stress.

5. The device of claim 1, wherein the second conductive region comprises material selected from the group consisting of Pt, Au, W, Mo, Ru, Ta, TaN, TiN, NiSi, CoSi, n+ polysilicon, p+ polysilicon, n+ poly SiGe, porous silicon, and p+ poly SiGe.

6. The device of claim 1, wherein the strain source comprises material selected from the group consisting of nitride, tungsten-silicide, amorphous silicon, poly SiGe, TaN, and TiN.

7. The device of claim 1, wherein the strain source comprises dislocation loops in at least one of the first and the second conductive regions.

8. The device of claim 2, wherein the charge injection filter comprises:

a first dielectric disposed adjacent to the second conductive region; and

a second dielectric disposed adjacent to the first dielectric, wherein the first dielectric has an energy band gap narrower than the second dielectric.

9. The device of claim 8, wherein the product of the dielectric constant of the first dielectric to the thickness of the second dielectric is substantially greater than the product of the dielectric constant of the second dielectric to the thickness of the first dielectric.

10. The device of claim 8, wherein the second dielectric comprises oxide, and the first dielectric comprises material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

11. The device of claim 8, wherein the second dielectric comprises oxynitride, and the first dielectric comprises material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, HfO₂—

SiO₂, and alloys formed thereof.

12. A method operating a semiconductor device having a first conductive region, a second conductive region disposed adjacent to and insulated from the first conductive region, a third conductive region disposed adjacent to and insulated from the second conductive region, and a strain source providing a mechanical stress to at least one of the first and the second conductive regions, the method comprising the steps of:

placing a first voltage on the first conductive region;

placing a second voltage on the second conductive region; and

placing a third voltage on the third conductive region to inject charge carriers from the first conductive region through the second conductive region into the third conductive region via piezo-ballistic-charge-injection mechanism.

13. The method of claim 12, wherein the charge carriers are electrons.

14. The method of claim 12, wherein the charge carriers are light-holes.

15. A method operating a nonvolatile memory cell having a plurality of states, the memory cell comprising a first conductive region, a second conductive region, a charge injection filter in between the first and the second conductive regions, a charge storage region disposed adjacent to and insulated from the second conductive region, a strain source providing a mechanical stress to at least one of the first and the second conductive regions, and spaced-apart source and drain regions of a first conductivity type in a body of a semiconductor of a second conductivity type, the method comprising the steps of:

applying a first voltage to the first conductive region;

applying a second voltage to the second conductive region;

applying a body voltage to the body;

applying a source voltage to the source region; and

applying a drain voltage to the drain region to establish one of the plurality of states of the memory cell by injecting ballistic charge carriers from the first conductive region through the second conductive region into the charge storage region via piezo-ballistic-charge-injection mechanism.

16. The method of claim 15, wherein the injection filter permits transporting of charge carriers of one polarity type from the first conductive region through the second conductive region to the charge storage region and blocks transporting of charge carriers of an opposite polarity type from the second conductive region to the first conductive region.

17. The method of claim 15, wherein the memory cell stores one of the plurality of states by storing a discrete amount of charges on the charge storage region.

18. The method of claim 15, wherein the body voltage, the source voltage, and the drain voltage are set at a first voltage setting to establish the memory cell in a first state of the plurality of states, and the method further comprises:

applying a second voltage setting to the body voltage, the source voltage, and the drain voltage to establish the memory cell in a second state of the plurality of states;

applying a third voltage setting to the body voltage, the source voltage, and the drain voltage to establish the memory cell in a third state of the plurality of states; and

applying a fourth voltage setting to the body voltage, the source voltage, and the drain voltage to establish the memory cell in a fourth state of the plurality of states.

19. The method of claim 18, wherein an amount of charges on the charge storage region in the first state is less than an amount of charges on the charge storage region in the second state, an amount of charges on the charge storage region in the second state is less than an amount of charges on the charge storage region in the third state, and an amount of charges on the charge storage region in the third state is less than an amount of charges on the charge storage region in the fourth state.

20. The method of claim 15, wherein the first voltage and the second voltage are set at a first voltage setting to establish the memory cell in a first state of the plurality of states, and the method further comprises:

applying a second voltage setting to the first voltage and the second voltage to establish the memory cell in a second state of the plurality of states;

applying a third voltage setting to the first voltage and the second voltage to establish the memory cell in a third state of the plurality of states; and

applying a fourth voltage setting to the first voltage and the second voltage to establish the memory cell in a fourth state of the plurality of states.

21. The method of claim 20, wherein an amount of charges on the charge storage region in the first state is less than an amount of charges on the charge storage region in the second state, an amount of charges on the charge storage region in the second state is less than an amount of charges on the charge storage region in the third state, and an amount of charges on the charge storage region in the third state is less than an amount of charges on the charge storage region in the fourth state.