NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20050201156A1
• Filed: 06/24/2004
• Published: 09/15/2005
• Est. Priority Date: 03/12/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tokiwa, Naoya
• Granted Patent: US 6,950,345 B1
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

A nonvolatile semiconductor memory device with a function of executing a verify operation for write data that is input from outside includes a memory cell array including memory cells arranged in a matrix, and a password storage area for storing password data, an input buffer that receives data input from outside, a first retaining circuit that retains input password data or write data, which is input to the input buffer, a verify sense amplifier that detects, at a time of the verify operation, the password data that is read out of the password storage area or data that is read out of the memory cell array, and a coincidence determination circuit that determines whether the input password data coincides with the read-out password data, or determines whether the write data coincides with the read-out data.

Claims

1. A nonvolatile semiconductor memory device with a function of executing a verify operation for write data, comprising:

a memory cell array including memory cells arranged in a matrix, and a password storage area for storing password data;

an input buffer that receives data input from outside;

a first retaining circuit that retains input password data or write data, which is input to the input buffer;

a verify sense amplifier that detects, at a time of the verify operation, the password data that is read out of the password storage area or data that is read out of the memory cell array; and

a coincidence determination circuit that determines whether the input password data coincides with the read-out password data, or determines whether the write data coincides with the read-out data.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the input password data comprises a plurality of input password data, and the coincidence determination circuit includes a plurality of coincidence determination circuits that correspond to said plurality of input password data.

3. The nonvolatile semiconductor memory device according to claim 2, wherein said plurality of input password data are successively input to the input buffer, and

said plurality of coincidence determination circuits successively determine whether the input password data coincide with the read-out password data that correspond to the input password data.

4. The nonvolatile semiconductor memory device according to claim 3, wherein each of the coincidence determination circuits executes determination when immediately prior input password data coincides.

5. The nonvolatile semiconductor memory device according to claim 2, wherein each of the coincidence determination circuits includes a second retaining circuit that retains a determination result.

6. The nonvolatile semiconductor memory device according to claim 5, further comprising a first output circuit that outputs a first coincidence signal when all of the second retaining circuits, which correspond to said plurality of input password data, show determination results of coincidence.

7. The nonvolatile semiconductor memory device according to claim 1, further comprising a command control circuit that causes the coincidence determination circuit to determine whether the input password data coincides with the read-out password data, on the basis of a first command that is input from outside.

8. The nonvolatile semiconductor memory device according to claim 3, further comprising a command control circuit that causes said plurality of coincidence determination circuits to successively determine whether said plurality of input password data coincide with said plurality of read-out password data, on the basis of a first command that is input from outside.

9. The nonvolatile semiconductor memory device according to claim 8, wherein the command control circuit causes the coincidence determination circuits to successively execute determination on the basis of a write enable signal that is input from outside along with the input password data.

10. The nonvolatile semiconductor memory device according to claim 2, further comprising an address buffer that receives a plurality of first addresses input from outside,

wherein each of the coincidence determination circuits determines whether the input password data corresponding to the first address coincides.

11. The nonvolatile semiconductor memory device according to claim 10, further comprising:

a first address generation circuit that generates a plurality of second addresses of said plurality of read-out password data; and

an address select circuit that selects said plurality of first addresses and said plurality of second addresses,

wherein each of the coincidence determination circuits determines whether the input password data corresponding to the first address coincides with the read-out password data corresponding to the second address.

12. The nonvolatile semiconductor memory device according to claim 11, wherein the first retaining circuit includes a plurality of first retaining circuits that correspond to said plurality of input password data.

13. The nonvolatile semiconductor memory device according to claim 12, further comprising:

a permission circuit that permits one of said plurality of first retaining circuits to retain the input password data, on the basis of the first address; and

a determination select circuit that selects one of said plurality of determination circuits, on the basis of the second address,

wherein each of the coincidence determination circuits, when permitted by permission circuit and selected by the determination select circuit, executes determination.

14. The nonvolatile semiconductor memory device according to claim 6, wherein the write data comprises a plurality of write data and includes a first data portion corresponding to said plurality of input password data and a second data portion that is greater than the first data portion,

the coincidence determination circuit includes a plurality of coincidence determination circuits corresponding to said plurality of write data, and

the device further comprises:

a second output circuit that outputs a second coincidence signal when all of the second retaining circuits corresponding to said plurality of write data show coincidence determination results; and

a write control circuit that executes re-write of only the second data portion when the second coincidence signal is not output and the first coincidence signal is output.

15. The nonvolatile semiconductor memory device according to claim 6, wherein the write data comprises a plurality of write data and includes a first data portion corresponding to said plurality of input password data and a second data portion that is greater than the first data portion,

the coincidence determination circuit includes a plurality of coincidence determination circuits corresponding to said plurality of write data, and

the device further comprises:

a third output circuit that outputs a third coincidence signal when all of the second retaining circuits corresponding to the second data portion show coincidence determination results; and

a write control circuit that executes re-write of only the first data portion when the first coincidence signal is not output and the third coincidence signal is output, and executes re-write of only the second data portion when the first coincidence signal is output and the third coincidence signal is not output.

16. The nonvolatile semiconductor memory device according to claim 14, further comprising a second address generation circuit that generates an address corresponding to the second data portion, when the second coincidence signal is not output and the first coincidence signal is output.

17. The nonvolatile semiconductor memory device according to claim 15, further comprising a second address generation circuit generates an address corresponding to the first data portion when the first coincidence signal is not output and the third coincidence signal is output, and generates an address corresponding to the second data portion when the first coincidence signal is output and the third coincidence signal is not output.

18. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a protect information memory circuit that stores information indicative of an area that is included in the memory cell array and is protected; and

a setting circuit that sets the device in a state in which rewrite is executable in the protect information memory circuit, when the input password data coincides with the read-out password data.