Method and apparatus for processing header bits and payload bits
First Claim
1. A method in a packet switched data transfer system for processing header bits and payload bits in a frame of bits, the method comprising:
- classifying the header bits into a first predetermined class of bits and into a second predetermined class of bits;
classifying the payload bits into the first predetermined class of bits and into the second predetermined class of bits;
processing the first predetermined class of bits in accordance with a first predetermined mechanism; and
processing the second predetermined class of bits in accordance with a second predetermined mechanism.
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Accused Products
Abstract
A method (200) and an apparatus (500) in a packet switched data transfer system for processing header bits and payload bits in a frame of bits are disclosed. The header bits are classified into a first predetermined class of bits and into a second predetermined class of bits (204), the payload bits are classified into the first predetermined class of bits and into the second predetermined class of bits (206), the first predetermined class of bits are processed in accordance with a first predetermined mechanism (208), and the second predetermined class of bits are processed in accordance with a second predetermined mechanism (210).
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Citations
19 Claims
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1. A method in a packet switched data transfer system for processing header bits and payload bits in a frame of bits, the method comprising:
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classifying the header bits into a first predetermined class of bits and into a second predetermined class of bits;
classifying the payload bits into the first predetermined class of bits and into the second predetermined class of bits;
processing the first predetermined class of bits in accordance with a first predetermined mechanism; and
processing the second predetermined class of bits in accordance with a second predetermined mechanism. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method in a packet switched data transfer system for reducing an encoded frame size a frame having header bits and payload bits, the method comprising:
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classifying the header bits into a first predetermined class of bits and into a second predetermined class of bits;
classifying the payload bits into the first predetermined class of bits and into the second predetermined class of bits;
encoding the first predetermined class of bits in accordance with a first encoding process; and
encoding the second predetermined class of bits in accordance with a second encoding process, wherein the first encoding process is different from the second encoding process. - View Dependent Claims (9, 10, 11)
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12. A method in a packet switched data transfer system for reformatting a frame having header bits and payload bits, the method comprising:
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classifying the header bits into a first predetermined class of bits and into a second predetermined class of bits;
classifying the payload bits into the first predetermined class of bits and into the second predetermined class of bits;
grouping the header bits of the first predetermined class of bits with the payload bits of the first predetermined class of bits;
grouping the header bits of the second predetermined class of bits with the payload bits of the second predetermined class of bits; and
constructing a reformatted frame using the grouped first predetermined class of bits and the grouped second predetermined class of bits. - View Dependent Claims (13, 14)
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15. A packet switched data transfer device comprising:
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a frame receiver configured to receive a frame of bits, the frame of bits comprising a plurality of header bits and a plurality of payload bits;
a bit classifier coupled to the frame receiver, the bit classifier configured to classify the plurality of header bits and the plurality of payload bits into a first class of bits and into a second class of bits; and
a bit processor coupled to the bit classifier, the bit processor configured to process the first class of bits according to a first predetermined process and to process the second class of bits according to a second predetermined process. - View Dependent Claims (16, 17, 18, 19)
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Specification