Parallel data link layer controllers in a network switching device

• US 20050201415A1
• Filed: 12/31/2003
• Published: 09/15/2005
• Est. Priority Date: 12/31/2003
• Status: Active Grant

• Current Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Original Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Inventors: Bailey, John, Narsinh, Anees
• Granted Patent: US 7,805,535 B2
• Time in Patent Office: Days
• US Class Current: 370/469
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/22 Traffic shaping
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/31 by tagging of packets, e.g. using discard eligibility [DE] bits
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 49/1523 Parallel switch fabric planes
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/503 Policing

Abstract

The present invention features a data link layer processor for performing VLAN tagging operations, policing, shaping, and statistics acquisition integrally with one or more media access controllers (MACs). When a plurality of data link layer processors are operated in parallel in a switching device, the computational burden carried by the route engine is significantly reduced. Moreover, the data link layer processor in its several embodiments may be used to introduce various forms of pre-processing and post-processing into network switching systems that employ route engines that do not posses such functionality.

Claims

1. A data link layer processor comprising:

one or more media access controllers (MACs);

a traffic shaper, operatively coupled to the one or more MACs, for discarding one or more frames that exceed a bandwidth requirement prior to transmission to the MACs.

2. A switching device comprising:

one or more physical layer interfaces for transmitting frames to a communication network;

a network processor for routing the frames towards the one or more physical layer interfaces; and

a plurality of data link layer processors, wherein each data link layer processor comprises;

one or more MACs, wherein each MAC is operatively coupled to a physical layer interface; and

a traffic shaper, operatively coupled to the one or more MACs, for discarding one or more frames from the network processor that exceed one or more bandwidth parameters prior to transmission to the MACs.

3. The switching device of claim 2, wherein the traffic shaper discards the one or more frames in accordance with a Three Color Marker (TCM) algorithm.

4. The switching device of claim 3, wherein the TCM algorithm is selected from the group consisting of:

single rate TCM, two rate TCM, and a combination thereof.

5. The switching device of claim 2, wherein the traffic shaper comprises:

an meter module for determining a flow rate associated with the frames received from the network processor; and

a discard control logic for selectively discarding said one or more frames based upon the flow rate and the one or more bandwidth parameters.

6. switching device of claim 5, wherein the traffic shaper further comprises a marker module for marking the plurality of frames in accordance with a TCM algorithm.

7. The switching device of claim 6, wherein the one or more bandwidth parameters comprise a committed information rate (CIR) and an excess burst size (EBS).

8. The switching device of claim 2, wherein the traffic shaper comprises a flow search engine for classifying frames from the network processor based upon one or more properties associated with the frames.

9. The switching device of claim 8, wherein the flow search engine comprises a content addressable memory (CAM).

10. The switching device of claim 8, wherein the CAM associated with each of the plurality of data link layer processors consists of QoS rules pertaining to the associated plurality of physical layer interfaces.

11. The switching device of claim 2, wherein data link layer processors are media access controller (MAC) processors.

12. The switching device of claim 2, wherein the switching device is selected from the group consisting of:

a router, a multi-layer switching device, and a switch blade.