Shift register and display device including the same

• US 20050201508A1
• Filed: 03/11/2005
• Published: 09/15/2005
• Est. Priority Date: 03/12/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Roh, Nam-Seok, Hong, Mun-Pyo, Park, Cheol-Woo, Shin, Kyong-Ju, Chae, Chong-Chul
• Granted Patent: US 8,107,586 B2
• Time in Patent Office: Days
• US Class Current: 377/10
• CPC Class Codes: G09G 2310/0281 Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register comprises stages connected to each other, in which each stage generates an output signal in response to any one of clock signals and an output from each of two different stages. Each clock signal has a duty ratio of less than 50% and a different phase from each of the other clock signals. A display device includes pixels, signal lines, and first and second shift registers each having stages connected to each other and generating output signals to signal lines. Each stage includes a set terminal, a reset terminal, a clock terminal, and first and second output terminals.

Claims

1. A shift register comprising a plurality of stages connected to each other, wherein each of the stages generates an output signal in response to any one of a plurality of clock signals and an output from each of two different stages, each of the clock signals having a duty ratio of less than 50% and a different phase from each of the other clock signals.

2. The shift register of claim 1, wherein each of the stages comprises:

a driving unit charging to a predetermined voltage in response to one of an output start signal and an output signal of a previous stage and generating the output signal in response to any one of the clock signals; and

a discharge unit discharging the predetermined voltage in response to an output signal of a next stage.

3. The shift register of claim 2, wherein the driving unit comprises:

an input unit which outputs a first voltage in response to one of an output start signal and an output signal of a previous stage; and

an output unit charging to a first voltage and generating the output signal in response to any one of the clock signals.

4. The shift register of claim 3, wherein the discharge unit outputs a second voltage to the output unit in response to the output signal of the next stage to discharge from the first voltage to the second voltage.

5. The shift register of claim 4, wherein the output unit outputs the second voltage as the output signal.

6. The shift register of claim 5, wherein the output unit comprises two output circuits having substantially a same structure.

7. The shift register of claim 3, wherein the output unit comprises two output circuits having substantially a same structure.

8. The shift register of claim 7, wherein each of the stages further comprises an output assistant unit transmitting the first voltage to the output unit in response to an output of the input unit.

9. The shift register of claim 8, wherein each stage has a set terminal, a reset terminal, a first output terminal and a second output terminal, and the input unit comprises a first switching element connected between the first voltage and a first point of contact and having a control terminal connected to the set terminal, and

the output assistant unit comprises:

a second switching element connected between the first voltage and a second point of contact; and

a third and a fourth switching elements connected in series between the first voltage and the second voltage,

wherein a control terminal of the second switching element is connected to a point of contact between the third and the fourth switching elements, and

the discharge unit comprises;

a fifth and a sixth switching elements connected in parallel between the first point of contact and the second voltage; and

a seventh and a eighth switching elements connected in parallel between the second point of contact and the second voltage,

wherein a control terminal of the fifth switching element is connected to the reset terminal, and a control terminal of the sixth switching element is connected to the second point of contact, and a control terminal of the seventh switching element is connected to the first point of contact, and a control terminal of the eighth switching element is connected to the set terminal, and

the output unit comprises;

a ninth switching element, a tenth switching element, an eleventh switching element and a twelfth switching element, the ninth and tenth switching elements being connected in series between the clock terminal and the second voltage, and the eleventh and twelfth switching elements being connected in series between the clock terminal and the second voltage; and

a first capacitor and a second capacitor connected between the first point of contact and the first and second output terminals, respectively,

wherein control terminals of the ninth and the eleventh switching elements are connected to the first point of contact and control terminals of the tenth and the eleventh switching elements are connected to the second point of contact,

wherein the first output terminal is connected to a point of contact between the ninth and tenth switching elements, and the second output terminal is connected to a point of contact between the eleventh and twelfth switching elements.

10. The shift register of claim 9, wherein the first to twelfth switching elements comprise amorphous silicon.

11. The shift register of claim 1, wherein the shift register comprises a first register unit and a second register unit, wherein the first register unit comprises first register unit stages, each of the first register unit stages is connected to a corresponding odd signal line, the second register unit comprises second register unit stages, and each of the second register unit stages is connected to a corresponding even signal line.

12. The shift register of claim 11, wherein each of the first register unit stages is connected to two different first register unit stages, and each of the second register unit stages is connected to two different second register unit stages.

13. The shift register of claim 11, wherein each of the first and second register unit stages has a first output terminal connected to an external unit and a second output terminal connected to another one of the first and second register unit stages.

14. The shift register of claim 13, wherein each of the first and second register unit stages has a set terminal and a reset terminal receiving an output from different ones of the first and second register unit stages.

15. The shift register of claim 11, wherein an initial first register unit stage in the first register unit and an initial second register unit stage in the second register unit each receive separate output start signals having a predetermined time interval.

16. The shift register of claim 11, wherein the plurality of the clock signals comprise a first clock signal and a second clock signal applied to the first register unit and a third clock signal and a fourth clock signal applied to the second register unit, and the first, second, third and fourth clock signals have a duty ratio of 25% and have a phase difference of 90 degrees, sequentially, and falling edges and rising edges of adjacent clock signals correspond.

17. A display device comprising:

pixels, each of the pixels comprising a switching element;

signal lines connected to each switching element; and

a first shift register and a second shift register comprising first shift register stages and second shift register stages, respectively, the first and second shift register stages being connected to each other and generating output signals for application to the signal lines,

wherein each of the first and second shift register stages has a set terminal, a reset terminal, a clock terminal, a first output terminal and a second output terminal, and

the set terminal is connected to a different stage second output terminal of another stage belonging to a same shift register, and the reset terminal is connected to another different stage second output terminal of still another stage belonging to the same shift register, the clock terminal is applied with one of clock signals, and the first output terminal is connected to one of the signal lines.

18. The display device of claim 17, wherein the first shift register is connected to odd signal lines and the second shift register is connected to even signal lines.

19. The display device of claim 18, wherein each of the clock signals has a duty ratio of 25% and has a different phase from each other one of the clock signals.

20. The display device of claim 18, wherein an initial first shift register stage in the first shift register and an initial second shift register stage in the second shift register each receive a first output start signal and a second output start signal, respectively, and the second output start signal is delayed by 1 H relative to the first output start signal.