Plating method

• US 20050202346A1
• Filed: 03/04/2005
• Published: 09/15/2005
• Est. Priority Date: 03/11/2004
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Yamano, Takaharu
• Granted Patent: US 7,790,359 B2
• Time in Patent Office: Days
• US Class Current: 430/300
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: G03F 7/2022 Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
• CPC Class Codes: G03F 7/203 comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

A method of forming an electrode on a semiconductor wafer by plating is disclosed that is able to reliably prevent leakage of a plating solution during the plating process. The plating method comprises the steps of forming a conductive layer on a semiconductor wafer; forming a negative resist layer on the conductive layer; exposing a center portion of the negative resist layer; exposing a peripheral region of the negative resist layer after the step of exposing the center portion of the negative resist layer; developing the exposed negative resist layer to form a predetermined plating pattern; and performing plating on the plating pattern.

Claims

1. A plating method, comprising the steps of:

forming a conductive layer on a semiconductor wafer;

forming a negative resist layer on the conductive layer;

exposing a center portion of the negative resist layer;

exposing a peripheral region of the negative resist layer after the step of exposing the center portion of the negative resist layer;

developing the exposed negative resist layer to form a predetermined plating pattern; and

performing plating on the plating pattern.

2. The method as claimed in claim 1, wherein the negative resist layer is thicker than 10 μ

m.

3. The method as claimed in claim 2, wherein the negative resist layer is formed from a dry film resist.

4. The method as claimed in claim 1, wherein in the step of performing plating, a sealing plating jig is used.

5. The method as claimed in claim 1, wherein in the step of exposing the center portion of the negative resist layer, a projection lithography stepper is used to expose the negative resist layer one unit region at a time.