Single-pole component manufacturing

• US 20050202636A1
• Filed: 04/27/2005
• Published: 09/15/2005
• Est. Priority Date: 12/22/1999
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Lanois, Frederic
• Granted Patent: US 7,220,644 B2
• Time in Patent Office: Days
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

The invention relates to a vertical-type single-pole component, comprising regions with a first type of conductivity which are embedded in a thick layer with a second type of conductivity. Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie an insulating material

Claims

1. A method of manufacturing a single-pole component of vertical type in a silicon substrate of a first conductivity type, comprising the steps of:

a) forming openings in a thick silicon layer of the first conductivity type covering the substrate, the thick silicon layer being more lightly doped than the substrate;

b) coating walls and bottoms of the openings with a silicon oxide layer;

c) forming, by implantation/diffusion through the bottoms of the openings, regions of a second conductivity type opposite to that of the substrate; and

d) filling the openings with an insulating material.

2. The method of claim 1, wherein, before step d), steps a), b) and c) are repeated at least once, with the openings being continued into the thick silicon layer.

3. The method of claim 2, wherein the thick silicon layer forms a cathode of a Schottky diode.

4. The method of claim 2, wherein the thick silicon layer forms a drain of a MOS transistor.

5. The method of claim 1, wherein the thick silicon layer forms a cathode of a Schottky diode.

6. The method of claim 1, wherein the thick silicon layer forms a drain of a MOS transistor.