Register move instruction for section select of source operand

• US 20050203928A1
• Filed: 03/04/2005
• Published: 09/15/2005
• Est. Priority Date: 03/04/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sankaran, Jagadeesh
• Granted Patent: US 7,376,813 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/355 Indexed addressing
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence

Abstract

A data processing apparatus execution unit includes a multiplexer having inputs receiving data from sections of a source data register or registers. The multiplexer selects data from one section to store in a destination data register. The execution unit may zero extend or sign extend the remaining most significant bits of the destination data. In an alternative embodiment, the execution unit includes plural multiplexers, one for each section of the destination data. Each multiplexer received data from each section of the source data register or registers. Special codes in the sections of the second source data register may select 0 fill, 1 fill or sign extension from the next most significant section for each multiplexer.

Claims

1. A data processing apparatus comprising:

a data register file including a plurality of data registers for storing data;

an execution unit having

an input connected to said data register file,

a multiplexer having a plurality of inputs receiving data from bits of corresponding equally sized sections of contiguous bits of said input, an output and a select input, said multiplexer coupling data from a selected one of said plurality of inputs corresponding to said select input to said output, and

an output having a contiguous section of least significant bits connected to said output of said multiplexer; and

an instruction decode unit responsive to received instructions, said instruction decode unit responsive to a received section select register move instruction to

supply data from an instruction specified one of said plurality of data registers to said input of said execution unit,

supply an instruction specified select input of said multiplexer, and

store data at said output of said execution unit in an instruction specified one of said plurality of data registers.

2. The data processing apparatus of claim 1, wherein:

said plurality of data registers of said data register file are denominated by register number;

said section select register move instruction includes a source register field designating a register number; and

said instruction decode unit is responsive to a received section select register move instruction to supply data from said data register denominated by said register number of said source register field to said input of said execution unit.

3. The data processing apparatus of claim 1, wherein:

said plurality of data registers of said data register file are denominated by register number;

said section select register move instruction includes a destination register field designating a register number; and

said instruction decode unit is responsive to a received section select register move instruction to store data at said output of said execution unit in a contiguous section of least significant bits of said data register denominated by said register number of said destination register field.

4. The data processing apparatus of claim 1, wherein:

said section select register move instruction includes an immediate data field designating one of said plurality sections; and

said instruction decode unit is responsive to a received section select register move instruction to supply said select input of said multiplexer corresponding to said immediate data field.

5. The data processing apparatus of claim 4, wherein:

said input includes two sections of contiguous bits;

said instruction decode unit is responsive to a received section select register move instruction to

supply a select input to said multiplexer to select a first section of said input upon a first coding of said immediate data field, and

supply a select input to said multiplexer to select a second section of said input upon a second coding of said immediate data field.

6. The data processing apparatus of claim 4, wherein:

said input includes four sections of contiguous bits;

said instruction decode unit is responsive to a received section select register move instruction to

supply a select input to said multiplexer to select a first section of said input upon a first coding of said immediate data field,

supply a select input to said multiplexer to select a second section of said input upon a second coding of said immediate data field,

supply a select input to said multiplexer to select a third section of said input upon a third coding of said immediate data field, and

supply a select input to said multiplexer to select a fourth section of said input upon a fourth coding of said immediate data field.

7. The data processing apparatus of claim 1, wherein:

said plurality of data registers of said data register file are denominated by register number;

said section select register move instruction includes a source register field designating a register number; and

said instruction decode unit is responsive to a received section select register move instruction to supply said select input of said execution unit corresponding to data stored in said data register denominated by said register number of said source register field.

8. The data processing apparatus of claim 7, wherein:

said input includes two sections of contiguous bits;

said instruction decode unit is responsive to a received section select register move instruction to

supply a select input to said multiplexer to select a first section of said input if said data register denominated by said register number of said source register field stores first data, and

supply a select input to said multiplexer to select a second section of said input if said data register denominated by said register number of said source register field stores second data.

9. The data processing apparatus of claim 7, wherein:

said input includes four sections of contiguous bits;

said instruction decode unit is responsive to a received section select register move instruction to

supply a select input to said multiplexer to select a first section of said input if said data register denominated by said register number of said source register field stores first data,

supply a select input to said multiplexer to select a second section of said input if said data register denominated by said register number of said source register field stores second data,

supply a select input to said multiplexer to select a third section of said input if said data register denominated by said register number of said source register field stores third data, and

supply a select input to said multiplexer to select a fourth section of said input if said data register denominated by said register number of said source register field stores fourth data.

10. The data processing apparatus of claim 1, wherein:

said execution unit supplies 0 to all bits of said output other than said contiguous section of least significant bits.

11. The data processing apparatus of claim 1, wherein:

said execution unit supplies a bit equal to a most significant bit of said selected one of said plurality of inputs to all bits of said output other than said contiguous section of least significant bits.

12. A data processing apparatus comprising:

a data register file including a plurality of data registers for storing data;

an execution unit having

a first input connected to said data register file,

a second input connected to said data register file,

a multiplexer having a plurality of inputs receiving data from bits of corresponding equally sized sections of contiguous bits of said first and second input, an output and a select input, said multiplexer coupling data from a selected one of said plurality of inputs corresponding to said select input to said output, and

an output having a contiguous section of least significant bits connected to said output of said multiplexer; and

an instruction decode unit responsive to received instructions, said instruction decode unit responsive to a received section select register move instruction to

supply data from a first instruction specified one of said plurality of data registers to said first input of said execution unit,

supply data from a second instruction specified one of said plurality of data registers to said second input of said execution unit,

supply an instruction specified select input of said multiplexer, and

store data at said output of said execution unit in an instruction specified one of said plurality of data registers.

13. The data processing apparatus of claim 12, wherein:

said plurality of data registers of said data register file are denominated by register number;

said section select register move instruction includes a source register field designating a register number; and

said instruction decode unit is responsive to a received section select register move instruction to

supply data from said data register denominated by said register number of said source register field to said first input of said execution unit, and

supply data from a data register corresponding to said data register denominated by said register number of said source register field to said second input of said execution unit.

14. The data processing apparatus of claim 13, wherein:

said data register corresponding to said data register denominated by said register number of said source register field is a data register denominated by a next sequential register number.

15. The data processing apparatus of claim 12, wherein:

said plurality of data registers of said data register file are denominated by register number;

said section select register move instruction includes a destination register field designating a register number; and

said instruction decode unit is responsive to a received section select register move instruction to store data at said output of said execution unit in a contiguous section of least significant bits of said data register denominated by said register number of said destination register field.

16. The data processing apparatus of claim 12, wherein:

said section select register move instruction includes an immediate data field designating one of said plurality sections; and

said instruction decode unit is responsive to a received section select register move instruction to supply said select input to said multiplexer corresponding to said immediate data field.

17. The data processing apparatus of claim 16, wherein:

said first and second inputs each include two sections of contiguous bits;

said instruction decode unit is responsive to a received section select register move instruction to

supply a select input to said multiplexer to select a first section of said first input upon a first coding of said immediate data field,

supply a select input to said multiplexer to select a second section of said first input upon a second coding of said immediate data field,

supply a select input to said multiplexer to select a first section of said second input upon a third coding of said immediate data field, and

supply a select input to said multiplexer to select a second section of said second input upon a fourth coding of said immediate data field.

18. The data processing apparatus of claim 16, wherein:

said first and second inputs each include four sections of contiguous bits;

said instruction decode unit is responsive to a received section select register move instruction to

supply a select input to said multiplexer to select a first section of said first input upon a first coding of said immediate data field,

supply a select input to said multiplexer to select a second section of said first input upon a second coding of said immediate data field,

supply a select input to said multiplexer to select a third section of said first input upon a third coding of said immediate data field,

supply a select input to said multiplexer to select a fourth section of said first input upon a fourth coding of said immediate data field,

supply a select input to said multiplexer to select a first section of said second input upon a fifth coding of said immediate data field,

supply a select input to said multiplexer to select a second section of said second input upon a sixth coding of said immediate data field,

supply a select input to said multiplexer to select a third section of said second input upon a seventh coding of said immediate data field, and

supply a select input to said multiplexer to select a fourth section of said second input upon an eighth coding of said immediate data field.

19. The data processing apparatus of claim 12, wherein:

said plurality of data registers of said data register file are denominated by register number;

said section select register move instruction includes a source register field designating a register number; and

said instruction decode unit is responsive to a received section select register move instruction to supply said select input of said multiplexer corresponding to data stored in said data register denominated by said register number of said source register field.

20. The data processing apparatus of claim 19, wherein:

said input includes two sections of contiguous bits;

said instruction decode unit is responsive to a received section select register move instruction to

supply a select input to said multiplexer to select a first section of said first input if said data register denominated by said register number of said source register field stores first data,

supply a select input to said multiplexer to select a second section of said first input if said data register denominated by said register number of said source register field stores second data,

supply a select input to said multiplexer to select a first section of said second input if said data register denominated by said register number of said source register field stores third data, and

supply a select input to said multiplexer to select a second section of said second input if said data register denominated by said register number of said source register field stores fourth data.

21. The data processing apparatus of claim 19, wherein:

said first and second inputs each include four sections of contiguous bits;

said instruction decode unit is responsive to a received section select register move instruction to

supply a select input to said multiplexer to select a first section of said first input if said data register denominated by said register number of said source register field stores first data,

supply a select input to said multiplexer to select a second section of said first input if said data register denominated by said register number of said source register field stores second data,

supply a select input to said multiplexer to select a third section of said first input if said data register denominated by said register number of said source register field stores third data,

supply a select input to said multiplexer to select a fourth section of said first input if said data register denominated by said register number of said source register field stores fourth data,

supply a select input to said multiplexer to select a first section of said second input if said data register denominated by said register number of said source register field stores fifth data,

supply a select input to said multiplexer to select a second section of said second input if said data register denominated by said register number of said source register field stores sixth data,

supply a select input to said multiplexer to select a third section of said second input if said data register denominated by said register number of said source register field stores seventh data, and

supply a select input to said multiplexer to select a fourth section of said second input if said data register denominated by said register number of said source register field stores eighth data.

22. The data processing apparatus of claim 12, wherein:

said execution unit supplies 0 to all bits of said output other than said contiguous section of least significant bits.

23. The data processing apparatus of claim 12, wherein:

said execution unit supplies a bit equal to a most significant bit of said selected one of said plurality of inputs to all bits of said output other than said contiguous section of least significant bits.

24. A data processing apparatus comprising:

a data register file including a plurality of data registers for storing data;

an execution unit having

an input connected to said data register file,

an output, and

a plurality of multiplexers, each having a plurality of inputs receiving data from bits of corresponding equally sized sections of contiguous bits of said input, an output and a select input, each multiplexer coupling data from a selected one of said plurality of inputs corresponding to said select input to a corresponding section of contiguous bits of said output, and

an instruction decode unit responsive to received instructions, said instruction decode unit responsive to a received multiple section select register move instruction to

supply data from an instruction specified one of said plurality of data registers to said input of said execution unit,

supply an instruction specified select input of each of said plurality of multiplexers, and

store data at said output said execution unit in an instruction specified one of said plurality of data registers.

25. The data processing apparatus of claim 24, wherein:

said plurality of data registers of said data register file are denominated by register number;

said section select register move instruction includes a source register field designating a register number; and

said instruction decode unit is responsive to a received multiple section select register move instruction to supply data from said data register denominated by said register number of said source register field to said input of said execution unit.

26. The data processing apparatus of claim 24, wherein:

said plurality of data registers of said data register file are denominated by register number;

said multiple section select register move instruction includes a destination register field designating a register number; and

said instruction decode unit is responsive to a received multiple section select register move instruction to store data at said output of said execution unit in a contiguous section of least significant bits of said data register denominated by said register number of said destination register field.

27. The data processing apparatus of claim 24, wherein:

said plurality of data registers of said data register file are denominated by register number;

said multiple section select register move instruction includes a source register field designating a register number; and

said instruction decode unit is responsive to a received multiple section select register move instruction to supply said select input of each of said plurality of multiplexers corresponding to data stored in a corresponding section of said data register denominated by said register number of said source register field.

28. The data processing apparatus of claim 27, wherein:

said input includes two sections of contiguous bits;

said instruction decode unit is responsive to a received multiple section select register move instruction to

supply a select input to each of said plurality of multiplexers to select a first section of said input if said corresponding section of said data register denominated by said register number of said source register field stores first data, and

supply a select input to each of said plurality of multiplexers to select a second section of said input if said corresponding section of said data register denominated by said register number of said source register field stores second data.

29. The data processing apparatus of claim 27, wherein:

said input includes four sections of contiguous bits;

said instruction decode unit is responsive to a received multiple section select register move instruction to

supply a select input to each of said plurality of multiplexers to select a first section of said input if said corresponding section of said data register denominated by said register number of said source register field stores first data,

supply a select input to each of said plurality of multiplexers to select a second section of said input if said corresponding section of said data register denominated by said register number of said source register field stores second data,

supply a select input to each of said plurality of multiplexers to select a third section of said input if said corresponding section of said data register denominated by said register number of said source register field stores third data, and

supply a select input to each of said plurality of multiplexers to select a fourth section of said input if said corresponding section of said data register denominated by said register number of said source register field stores fourth data.

30. The data processing apparatus of claim 27, wherein:

said execution unit supplies 0 to all bits of a section of said output if said corresponding section of said data register denominated by said register number of said source register field stores an all 0 special code.

31. The data processing apparatus of claim 27, wherein:

said execution unit supplies 1 to all bits of a section of said output if said corresponding section of said data register denominated by said register number of said source register field stores an all 1 special code.

32. The data processing apparatus of claim 27, wherein:

said execution unit supplies a bit equal to a most significant bit of a next less significant section to all bits of a section of said output if said corresponding section of said data register denominated by said register number of said source register field stores a sign extend special code.

33. A data processing apparatus comprising:

a data register file including a plurality of data registers for storing data;

an execution unit having

a first input connected to said data register file,

a second input connected to said data register file,

an output, and

a plurality of multiplexers, each having a plurality of inputs receiving data from bits of corresponding equally sized sections of contiguous bits of said first and second inputs, an output and a select input, each multiplexer coupling data from a selected one of said plurality of inputs corresponding to said select input to a corresponding section of contiguous bits of said output, and

an instruction decode unit responsive to received instructions, said instruction decode unit responsive to a received multiple section select register move instruction to

supply data from a first instruction specified one of said plurality of data registers to said first input of said execution unit,

supply data from a second instruction specified one of said plurality of data registers to said second input of said execution unit,

supply an instruction specified select input to each of said plurality of multiplexers, and

store data at said output of said execution unit in an instruction specified one of said plurality of data registers.

34. The data processing apparatus of claim 33, wherein:

said plurality of data registers of said data register file are denominated by register number;

said multiple section select register move instruction includes a source register field designating a register number; and

said instruction decode unit is responsive to a received section select register move instruction to

supply data from said data register denominated by said register number of said source register field to said first input of said execution unit, and

supply data from a data register corresponding to said data register denominated by said register number of said source register field to said second input of said execution unit.

35. The data processing apparatus of claim 34, wherein:

said data register corresponding to said data register denominated by said register number of said source register field is a data register denominated by a next sequential register number.

36. The data processing apparatus of claim 33, wherein:

said plurality of data registers of said data register file are denominated by register number;

said multiple section select register move instruction includes a destination register field designating a register number; and

said instruction decode unit is responsive to a received multiple section select register move instruction to store data at said output of said execution unit in said data register denominated by said register number of said destination register field.

37. The data processing apparatus of claim 33, wherein:

said plurality of data registers of said data register file are denominated by register number;

said multiple section select register move instruction includes a source register field designating a register number; and

said instruction decode unit is responsive to a received multiple section select register move instruction to supply said select input of each of said plurality of multiplexers corresponding to data stored in said corresponding section of said data register denominated by said register number of said source register field.

38. The data processing apparatus of claim 37, wherein:

said input includes two sections of contiguous bits;

said instruction decode unit is responsive to a received multiple section select register move instruction to

supply a select input to each of said plurality of multiplexers to select a first section of said first input if said corresponding section of said data register denominated by said register number of said source register field stores first data,

supply a select input to each of said plurality of multiplexers to select a second section of said first input if said corresponding section of said data register denominated by said register number of said source register field stores second data,

supply a select input to each of said plurality of multiplexers to select a first section of said second input if said corresponding section of said data register denominated by said register number of said source register field stores first data, and

supply a select input to each of said plurality of multiplexers to select a second section of said second input if said corresponding section of said data register denominated by said register number of said source register field stores second data.

39. The data processing apparatus of claim 37, wherein:

said input includes four sections of contiguous bits;

said instruction decode unit is responsive to a received multiple section select register move instruction to

supply a select input to each of said plurality of multiplexers to select a first section of said first input if said corresponding section of said data register denominated by said register number of said source register field stores first data,

supply a select input to each of said plurality of multiplexers to select a second section of said first input if said corresponding section of said data register denominated by said register number of said source register field stores second data,

supply a select input to each of said plurality of multiplexers to select a third section of said first input if said corresponding section of said data register denominated by said register number of said source register field stores third data,

supply a select input to each of said plurality of multiplexers to select a fourth section of said first input if said corresponding section of said data register denominated by said register number of said source register field stores fourth data,

supply a select input to each of said plurality of multiplexers to select a first section of said second input if said corresponding section of said data register denominated by said register number of said source register field stores fifth data,

supply a select input to each of said plurality of multiplexers to select a second section of said second input if said corresponding section of said data register denominated by said register number of said source register field stores sixth data,

supply a select input to each of said plurality of multiplexers to select a third section of said second input if said corresponding section of said data register denominated by said register number of said source register field stores seventh data, and

supply a select input to each of said plurality of multiplexers to select a fourth section of said second input if said corresponding section of said data register denominated by said register number of said source register field stores eighth data.

40. The data processing apparatus of claim 37, wherein:

said execution unit supplies 0 to all bits of a section of said output if said corresponding section of said data register denominated by said register number of said source register field stores an all 0 special code.

41. The data processing apparatus of claim 37, wherein:

said execution unit supplies 1 to all bits of a section of said output if said corresponding section of said data register denominated by said register number of said source register field stores an all 1 special code.

42. The data processing apparatus of claim 37, wherein:

said execution unit supplies a bit equal to a most significant bit of a next less significant section to all bits of a section of said output if said corresponding section of said data register denominated by said register number of said source register field stores a sign extend special code.