Random number source and associated methods

• US 20050203979A1
• Filed: 03/11/2004
• Published: 09/15/2005
• Est. Priority Date: 03/11/2004
• Status: Active Grant

• Current Assignee: Harris Global Communications, Inc. (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Kurdziel, Michael Thomas, Clements, Robert Paul
• Granted Patent: US 7,293,054 B2
• Time in Patent Office: Days
• US Class Current: 708/251
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords

Abstract

A random number source includes a ring oscillator generating an internal clock signal having random phase noise, and a first linear feedback shift register connected to the ring oscillator. A counter is connected to a first tap of the first linear feedback shift register for generating a count signal. A feedback bit controller is connected to a second tap of the first linear feedback shift register for generating a random feedback bit for a time based upon the count signal. A second linear feedback shift register is connected to the feedback bit controller for generating a random number based upon the random feedback bit.

Claims

1. A random number source comprising:

a ring oscillator generating an internal clock signal having random phase noise;

a first linear feedback shift register connected to said ring oscillator and comprising a plurality of taps;

a counter connected to at least one first tap of said first linear feedback shift register for generating a count signal;

a feedback bit controller connected to a second tap of said first linear feedback shift register for generating a random feedback bit for a time based upon the count signal; and

a second linear feedback shift register connected to said feedback bit controller for generating a random number based upon the random feedback bit.

2. A random number source according to claim 1 further comprising a system clock connected to said ring oscillator, said feedback bit controller and said first linear feedback shift register.

3. A random number source according to claim 2 wherein a frequency of the internal clock signal is greater than a frequency of a system clock signal.

4. A random number source according to claim 2 wherein a frequency of the internal clock signal is not an integer multiple of a frequency of a system clock signal.

5. A random number source according to claim 1 wherein said second linear feedback shift register comprises a feedback path;

and wherein said feedback bit controller is connected to the feedback path for inputting the random feedback bit into the feedback path.

6. A random number source according to claim 5 wherein said counter defines the time that the feedback bit is input into the feedback path based upon a count cycle of said counter.

7. A random number source according to claim 6 wherein the time is random for each count cycle.

8. A random number source according to claim 1 wherein said first linear feedback shift register comprises n bits, and said second linear feedback shift register comprises m bits, with n being between 20 and 60, and m being between 40 and 80.

9. An encryption device comprising:

a random number source for generating a random number and comprising

a ring oscillator generating an internal clock signal having random phase noise,

a first linear feedback shift register connected to said ring oscillator and comprising a plurality of taps,

a counter connected to at least one first tap of said first linear feedback shift register for generating a count signal,

a feedback bit controller connected to a second tap of said first linear feedback shift register for generating a random feedback bit for a time based upon the count signal, and

a second linear feedback shift register connected to said feedback bit controller for generating the random number based upon the random feedback bit; and

a cryptographic key generator connected to said random number source and generating an output signal based upon the random umber.

10. An encryption device according to claim 9 wherein the output signal includes at least one of random cryptographic keys, randomization vectors for an initial state of a cryptographic session, and initialization vectors for a cryptographic session.

11. An encryption device according to claim 9 further comprising a system clock connected to said ring oscillator, said feedback bit controller and said first linear feedback shift register.

12. An encryption device according to claim 11 wherein a frequency of the internal clock signal is greater than a frequency of a system clock signal.

13. An encryption device according to claim 11 wherein a frequency of the internal clock signal is not an integer multiple of a frequency of a system clock signal.

14. An encryption device according to claim 9 wherein said second linear feedback shift register comprises a feedback path;

and wherein said feedback bit controller is connected to the feedback path for inputting the random feedback bit into the feedback path.

15. An encryption device according to claim 14 wherein said counter defines the time that the feedback bit is input into the feedback path based upon a count cycle of said counter.

16. An encryption device according to claim 15 wherein the time is random for each count cycle.

17. An encryption device according to claim 9 wherein said first linear feedback shift register comprises n bits, and said second linear feedback shift register comprises m bits, with n being between 20 and 60, and m being between 40 and 80.

18. An encryption device according to claim 9 further comprising a portable housing containing said random number source and said cryptographic key generator.

19. An electronic device comprising:

a random number source for generating a random number and comprising

a ring oscillator generating an internal clock signal having random phase noise,

a first linear feedback shift register connected to said ring oscillator and comprising a plurality of taps,

a counter connected to at least one first tap of said first linear feedback shift register for generating a count signal,

a feedback bit controller connected to a second tap of said first linear feedback shift register for generating a random feedback bit for a time based upon the count signal, and

a second linear feedback shift register connected to said feedback bit controller for generating the random number based upon the random feedback bit; and

other circuitry connected to said random number source for performing a desired operation based on the random number.

20. An electronic device according to claim 19 wherein the desired operation is a smart card operation.

21. An electronic device according to claim 19 wherein the desired operation is an electronic gaming operation.

22. An electronic device according to claim 19 further comprising a system clock connected to said ring oscillator, said feedback bit controller and said first linear feedback shift register.

23. An electronic device according to claim 22 wherein a frequency of the internal clock signal is greater than a frequency of a system clock signal.

24. An electronic device according to claim 22 wherein a frequency of the internal clock signal is not an integer multiple of a frequency of a system clock signal.

25. An electronic device according to claim 19 wherein said second linear feedback shift register comprises a feedback path;

and wherein said feedback bit controller is connected to the feedback path for inputting the random feedback bit into the feedback path.

26. An electronic device according to claim 25 wherein said counter defines the time that the feedback bit is input into the feedback path based upon a count cycle of said counter.

27. An electronic device according to claim 26 wherein the time is random for each count cycle.

28. An electronic device according to claim 19 wherein said first linear feedback shift register comprises n bits, and said second linear feedback shift register comprises m bits, with n being between 20 and 60, and m being between 40 and 80.

29. An encryption device according to claim 19 further comprising a portable housing containing said random number source and said other circuitry.

30. A method for generating a random number comprising:

generating an internal clock signal having random phase noise using a ring oscillator;

providing the internal clock signal to a first linear feedback shift register;

generating a count signal using a counter connected to at least one first tap of the first linear feedback shift register;

generating a random feedback bit for a time based upon the count signal using a feedback bit controller connected to a second tap of the first linear feedback shift register; and

generating the random number based upon the random feedback bit using a second linear feedback shift register connected to the feedback bit controller.

31. A method according to claim 30 further comprising using the random number in a cryptographic key generator.

32. A method according to claim 30 further comprising using the random number in a smart card.

33. A method according to claim 30 further comprising using the random number in an electronic gaming device.

34. A method according to claim 30 further comprising providing system clock signals to the ring oscillator, the feedback bit controller and the first linear feedback shift register.

35. A method according to claim 34 wherein a frequency of the internal clock signal is greater than a frequency of a system clock signal.

36. A method according to claim 34 wherein a frequency of the internal clock signal is not an integer multiple of a frequency of a system clock signal.

37. A method according to claim 30 wherein the second linear feedback shift register comprises a feedback path;

and further comprising inputting the random feedback bit into the feedback path.

38. A method according to claim 37 wherein the counter defines the time that the feedback bit is input into the feedback path based upon a count cycle of the counter.