Non-volatile memory with synchronous DRAM interface
First Claim
1. A non-volatile memory device comprising:
- a non-volatile memory array;
a buffer memory;
a synchronous memory interface; and
a controller coupled to the non-volatile memory array, the buffer memory, and the synchronous memory interface, wherein the controller is adapted to interface to and manage the non-volatile memory array and buffer memory and to present the non-volatile memory device as a synchronous memory device through the synchronous memory interface.
1 Assignment
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Accused Products
Abstract
A high density non-volatile memory system, card, and device is described that incorporates a synchronous interface. This is accomplished through use of an external or embedded controller and/or memory buffer to manage the high density non-volatile memory device(s) to present it as a conventional memory device having a synchronous interface that is accessible by row and column address. This allows the high density non-volatile memory to support in-place code execution and allows it to be booted from. Additionally, this incorporation eliminates the overhead of drivers and/or operating system support required to utilize and present conventional high density non-volatile memory devices and moves it internal to the memory device. This simplifies the use and design effort in the overhead and specialized interfacing of high density non-volatile memories and in particular, NAND architecture Flash memories, while reducing the production cost through use of less expensive high density non-volatile memory.
213 Citations
99 Claims
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1. A non-volatile memory device comprising:
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a non-volatile memory array;
a buffer memory;
a synchronous memory interface; and
a controller coupled to the non-volatile memory array, the buffer memory, and the synchronous memory interface, wherein the controller is adapted to interface to and manage the non-volatile memory array and buffer memory and to present the non-volatile memory device as a synchronous memory device through the synchronous memory interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A NAND architecture Flash memory device comprising:
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a NAND architecture Flash memory array;
a buffer memory;
a synchronous memory interface; and
a controller coupled to the NAND architecture Flash memory array, the buffer memory, and the synchronous memory interface, wherein the controller is adapted to interface to and manage the NAND architecture Flash memory array and to portray the NAND architecture Flash memory device as a synchronous memory device through the synchronous memory interface. - View Dependent Claims (23, 24, 25, 26)
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27. A non-volatile memory subsystem comprising:
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one or more non-volatile memory devices;
a buffer memory;
a synchronous memory interface; and
a controller coupled to the one or more non-volatile memory devices, the buffer memory, and the synchronous memory interface, wherein the controller is adapted to interface to and manage the non-volatile memory devices and to present the non-volatile memory devices as a synchronous memory device through the synchronous memory interface. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. A system comprising:
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a host; and
one or more non-volatile memory devices coupled to the host, wherein each of the one or more non-volatile memory devices comprises, a non-volatile memory array;
a buffer memory;
a synchronous memory interface; and
a controller coupled to the non-volatile memory array, the buffer memory, and the synchronous memory interface, wherein the controller is adapted to interface to and manage the non-volatile memory array and to present the non-volatile memory device as a synchronous memory device through the synchronous memory interface. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59)
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60. A method of operating a non-volatile memory device comprising:
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managing the non-volatile memory device with an internal controller;
presenting the non-volatile memory device as a synchronous memory device through a synchronous memory interface; and
buffering data access requests received through the synchronous memory interface in an internal buffer memory. - View Dependent Claims (61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74)
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75. A method of operating a NAND architecture Flash memory device comprising:
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managing the NAND architecture Flash memory device with an internal controller;
presenting the NAND architecture Flash memory device as a synchronous memory device through a synchronous memory interface; and
buffering data access requests received through the synchronous memory interface in an internal buffer memory. - View Dependent Claims (76, 77, 78)
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79. A method of operating a non-volatile memory subsystem comprising:
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managing one or more non-volatile memory devices with a controller;
presenting the one or more non-volatile memory devices as a synchronous memory device through a synchronous memory interface; and
buffering data access requests received through the synchronous memory interface in a buffer memory. - View Dependent Claims (80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93)
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94. A machine-usable medium, the machine-usable medium containing a software routine for causing a memory controller to execute a method, wherein the method comprises:
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managing one or more non-volatile memory devices with the memory controller;
presenting one or more non-volatile memory devices as a synchronous memory device through a synchronous memory interface; and
buffering data access requests received through the synchronous memory interface in a buffer memory. - View Dependent Claims (95)
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96. A system comprising:
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a host; and
one or more non-volatile memory devices coupled to the host, wherein each of the one or more non-volatile memory devices comprises, a non-volatile memory array;
a buffer memory; and
a synchronous memory interface, wherein the non-volatile memory devices comprises a means for interfacing with, managing, and buffering data access to the non-volatile memory array and comprises a means for presenting the non-volatile memory device as a synchronous memory device through the synchronous memory interface. - View Dependent Claims (97)
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98. A NAND architecture Flash memory subsystem comprising:
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one or more NAND architecture Flash memory devices;
a buffer memory;
a synchronous memory interface; and
a controller coupled to the one or more NAND architecture Flash memory devices, the buffer memory, and the synchronous memory interface, wherein the controller is adapted to interface to and manage the NAND architecture Flash memory devices and to present the NAND architecture Flash memory devices as a synchronous memory device through the synchronous memory interface.
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99. A method of operating a NAND architecture Flash memory subsystem comprising:
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managing one or more NAND architecture Flash memory devices with a controller;
presenting the one or more NAND architecture Flash memory devices as a synchronous memory device through a synchronous memory interface; and
buffering data access requests received through the synchronous memory interface in a buffer memory.
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Specification