Random number test circuit, random number generation circuit, semiconductor integrated circuit, IC card and information terminal device
First Claim
Patent Images
1. A random number test circuit comprising:
- a counting unit configured to count number of repetitions of a certain-vasue bit in a random number sequence, the repetitions occurring in series;
a detecting unit configured to detect a plurality of numbers corresponding to a kind of bits in the random number sequence; and
a determining unit configured to determine whether the random number sequence is normal, based on the numbers.
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Abstract
A random number test circuit includes a counting unit to count number of repetitions of a certain-value bit in a random number sequence, the repetitions occurring in series, a detecting unit to detect a plurality of numbers corresponding to a kind of bits in the random number sequence, and a determining unit to determine whether the random number sequence is normal, based on the numbers.
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Citations
15 Claims
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1. A random number test circuit comprising:
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a counting unit configured to count number of repetitions of a certain-vasue bit in a random number sequence, the repetitions occurring in series;
a detecting unit configured to detect a plurality of numbers corresponding to a kind of bits in the random number sequence; and
a determining unit configured to determine whether the random number sequence is normal, based on the numbers. - View Dependent Claims (2)
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3. A random number test circuit comprising:
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a receiving unit configured to receive a random number sequence;
a detection circuit configured to detect a plurality of bit data items of “
1”
or “
0”
in the random number sequence;
a shift register which holds in series the bit data items of “
1”
or “
0”
repeated in the random number sequence, based on the detected bit data items;
a register which holds, based on the detected bit data items, a content of the shift register when each of the bit data items is switched from “
1”
to “
0”
or from “
0”
to “
1”
; and
a determination circuit configured to determine types of repetitions of the bit data items of “
1”
or “
0”
from the held content. - View Dependent Claims (4, 5, 6, 7)
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8. A random number test circuit comprising:
-
a receiving unit configured to receive a random number sequence;
a detection circuit configured to detect a plurality of bit data items of “
1” and
“
0”
in the random number sequence;
a plurality of shift registers which hold in series the bit data items of “
1” and
“
0”
repeated in the random number sequence, based on the detected bit data items;
a register which holds, based on the detected bit data items, a plurality of contents of the shift registers when the bit data items are switched from “
1” and
“
0”
to “
0” and
“
1”
, respectively; and
a determination circuit configured to determine types of repetitions of the bit data items “
1” and
“
0”
from the held contents. - View Dependent Claims (9, 10, 11, 12)
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13. A semiconductor integrated circuit device comprising:
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a generation unit configured to generate a random number sequence;
a random number test circuit which tests the random number sequence supplied from the generation unit, and generates a test signal; and
an output terminal which outputs the test signal;
wherein the random number test circuit includes;
a receiving unit configured to receive the random number sequence;
a detection circuit configured to detect a plurality of bit data items of “
1” and
“
0”
in the random number sequence;
a plurality of shift registers which hold in series the bit data items of “
1” and
“
0”
repeated in the random number sequence, based on the detected bit data items;
a register which holds, based on the detected bit data items, a plurality of contents of the shift registers when the bit data items are switched from “
1” and
“
0”
to “
0” and
“
1”
, respectively; and
a determination circuit configured to determine types of repetitions of the bit data items “
1” and
“
0”
from the held contents.
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14. An integrated circuit card provided with a semiconductor integrated circuit, the semiconductor integrated circuit comprising:
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a generation unit configured to generate a random number sequence;
a random number test circuit which tests the random number sequence supplied from the generation unit, and generates a test signal; and
an output terminal which outputs the test signal;
wherein the random number test circuit includes;
a receiving unit configured to receive the random number sequence;
a detection circuit configured to detect a plurality of bit data items of “
1” and
“
0”
in the random number sequence;
a plurality of shift registers which hold in series the bit data items of “
1” and
“
0”
repeated in the random number sequence, based on the detected bit data items;
a register which holds, based on the detected bit data items, a plurality of contents of the shift registers when the bit data items are switched from “
1” and
“
0”
to “
0” and
“
1”
, respectively; and
a determination circuit configured to determine types of repetitions of the bit data items “
1” and
“
0”
from the held contents.
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15. An information terminal device provided with a semiconductor integrated circuit, the semiconductor integrated circuit comprising:
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a generation unit configured to generate a random number sequence;
a random number test circuit which tests the random number sequence supplied from the generation unit, and generates a test signal; and
an output terminal which outputs the test signal;
wherein the random number test circuit includes;
a receiving unit configured to receive the random number sequence;
a detection circuit configured to detect a plurality of bit data items of “
1” and
“
0”
in the random number sequence;
a plurality of shift registers which hold in series the bit data items of “
1” and
“
0”
repeated in the random number sequence, based on the detected bit data items;
a register which holds, based on the detected bit data items, a plurality of contents of the shift registers when the bit data items are switched from “
1” and
“
0”
to “
0” and
“
1”
, respectively; and
a determination circuit configured to determine types of repetitions of the bit data items “
1” and
“
0”
from the held contents.
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsAbe, Keiko, Yasuda, Shinichi, Fujita, Shinobu, Fujisaki, Koichi, Tanamoto, Tetsufumi
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Application NumberUS11/067,672Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current714/724CPC Class CodesG01R 31/3181 Functional testing G01R31/3...G06F 7/58 Random or pseudo-random num...
