Layout data verification method, mask pattern verification method and circuit operation verification method

• US 20050204327A1
• Filed: 03/11/2005
• Published: 09/15/2005
• Est. Priority Date: 03/11/2004
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ohashi, Tatsuo, Itou, Mitsumi, Tsujikawa, Hiroyuki, Mukai, Kiyohito, Ozoe, Ritsuko
• Application Number:
  US11/076,939
• Publication Number:
  US 20050204327A1
• Time in Patent Office: Days
• US Class Current: 716/52
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions

Abstract

In the verification method of the present invention, a defect that is to cause a problem in fabrication is extracted from a mask pattern. The mask pattern is one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern. The verification method includes the steps of: determining the exposure dose in the photolithography process; simulating the photolithography process on a computer based on the determined exposure dose; checking whether or not the desired design pattern has been obtained; and locating a fault point and outputting the result.

Claims

1. A mask pattern verification method as a verification method of extracting from a mask pattern a defect that is to cause a problem in fabrication, the mask pattern being one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern, the verification method comprising the steps of:

a step (a) of determining the parameter in the photolithography process;

a step (b) of simulating the photolithography process on a computer based on the determined parameter;

a step (c) of checking whether or not the desired design pattern has been obtained; and

a step (d) of locating a fault point and outputting the result.

2. The mask pattern verification method of claim 1, wherein the exposure dose in the photolithography process is determined in the step (a), and

the photolithography process is simulated on a computer based on the determined exposure dose in the step (b).

3. The mask pattern verification method of claim 1, wherein the focal point in the photolithography process is determined in the step (a), and

the photolithography process is simulated on a computer based on the determined focal point in the step (b).

4. The mask pattern verification method of claim 1, wherein the exposure dose and the focal point in the photolithography process are determined in the step (a), and

the photolithography process is simulated on a computer based on the determined exposure dose and the determined focal point in the step (b).

5. The mask pattern verification method of claim 1, further comprising the step of:

a step (e) of simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface,

wherein the exposure dose in the photolithography process is determined in the step (a), and

the photolithography process is simulated on a computer based on the simulated steps and the determined exposure dose in the step (b).

6. The mask pattern verification method of claim 1, further comprising the step of:

a step (e) of simulating steps formed on a silicon wafer surface on a computer from a density distribution of the semiconductor circuit pattern on the silicon wafer surface,

wherein the focal point in the photolithography process is determined in the step (a), and

the photolithography process is simulated on a computer based on the simulated steps and the determined focal point in the step (b).

7. The mask pattern verification method of claim 1, further comprising the step of:

a step (e) of simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface,

wherein the exposure dose and the focal point in the photolithography process are determined in the step (a), and

the photolithography process is simulated on a computer based on the simulated steps, the determined exposure dose, and the determined focal point in the step (b).

8. The mask pattern verification method of claim 1, further comprising the steps of:

a step (f) of simulating a defect factor occurring with a given probability in fabrication on a computer; and

a step (g) of simulating the yield on a computer based on the simulation result of the photolithography process and the simulation result of the defect factor.

9. The mask pattern verification method of claim 8, further comprising the steps of:

a step (h) of extracting circuit information from a transferred image obtained from the result of the simulation; and

a step (i) of simulating circuit operation using the circuit information.

10. The mask pattern verification method of claim 1, further comprising the step of

a step (j) of shrinking the mask pattern uniformly,

wherein the photolithography process is simulated for the mask pattern shrunk in the step (j) on a computer based on the determined parameter in the step (b).

11. The mask pattern verification method of claim 10, further comprising the steps of:

a step (k) of simulating a defect factor occurring with a given probability in fabrication on a computer; and

a step (l) of simulating the yield on a computer based on the simulation result of the photolithography process and the simulation result of the defect factor.

12. The mask pattern verification method of claim 11, further comprising the steps of:

a step (m) of extracting circuit information from a transferred image obtained from the result of the simulation; and

a step (n) of simulating circuit operation using the circuit information.

13. A circuit information extraction method as a method for extracting circuit information that imitates a semiconductor integrated circuit in its operation, using a mask pattern obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern, the method comprising the steps of:

a step (a) of determining the parameter in the photolithography process;

a step (b) of simulating the photolithography process on a computer based on the determined parameter;

a step (c) of extracting circuit information from a transferred image obtained from the result of the simulation; and

a step (d) of locating a fault point and outputting the result.

14. The circuit information extraction method of claim 13, wherein the exposure dose in the photolithography process is determined in the step (a), and

the photolithography process is simulated on a computer based on the determined exposure dose in the step (b).

15. The circuit information extraction method of claim 13, wherein the focal point in the photolithography process is determined in the step (a), and

the photolithography process is simulated on a computer based on the determined focal point in the step (b).

16. The circuit information extraction method of claim 13, wherein the exposure dose and the focal point in the photolithography process are determined in the step (a), and

the photolithography process is simulated on a computer based on the determined exposure dose and the determined focal point in the step (b).

17. The circuit information extraction method of claim 13, further comprising the step of:

a step (e) of simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface,

wherein the exposure dose in the photolithography process is determined in the step (a), and

the photolithography process is simulated on a computer based on the simulated steps and the determined exposure dose in the step (b).

18. The circuit information extraction method of claim 13, further comprising the step of:

a step (e) of simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface,

wherein the focal point in the photolithography process is determined in the step (a), and

the photolithography process is simulated on a computer based on the simulated steps and the determined focal point in the step (b).

19. The circuit information extraction method of claim 13, further comprising the step of:

a step (e) of simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface,

wherein the exposure dose and the focal point in the photolithography process are determined in the step (a), and

the photolithography process is simulated on a computer based on the simulated steps, the determined exposure dose, and the determined focal point in the step (b).

20. A circuit information extraction method as a method for extracting circuit information that imitates a semiconductor integrated circuit in its operation, the method comprising the steps of:

a step (a) of shrinking uniformly a mask pattern obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern;

a step (b) of determining the parameter in the photolithography process;

a step (c) of simulating the photolithography process for the mask pattern shrunk in the step (a) on a computer based on the determined parameter;

a step (d) of extracting circuit information from a transferred image obtained from the result of the simulation; and

a step (e) of locating a fault point and outputting the result.

21. The circuit information extraction method of claim 20, wherein the exposure dose in the photolithography process is determined in the step (b), and

the photolithography process is simulated for the mask pattern shrunk in the step (a) on a computer based on the determined exposure dose in the step (c).

22. The circuit information extraction method of claim 20, wherein the focal point in the photolithography process is determined in the step (b), and

the photolithography process is simulated for the mask pattern shrunk in the step (a) on a computer based on the determined focal point in the step (c).

23. The circuit information extraction method of claim 20, wherein the exposure dose and the focal point in the photolithography process are determined in the step (b), and

the photolithography process is simulated for the mask pattern shrunk in the step (a) on a computer based on the determined exposure dose and the determined focal point in the step (c).

24. The circuit information extraction method of claim 20, further comprising the step of:

a step (f) of simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface,

wherein the exposure dose in the photolithography process is determined in the step (b), and

the photolithography process is simulated for the mask pattern shrunk in the step (a) on a computer based on the simulated steps and the determined exposure dose in the step (c).

25. The circuit information extraction method of claim 20, further comprising the step of:

a step (f) of simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface,

wherein the focal point in the photolithography process is determined in the step (b), and

the photolithography process is simulated for the mask pattern shrunk in the step (a) on a computer based on the simulated steps and the determined focal point in the step (c).

26. The circuit information extraction method of claim 20, further comprising the step of:

a step (f) of simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface,

wherein the exposure dose and the focal point in the photolithography process are determined in the step (b), and

the photolithography process is simulated for the mask pattern shrunk in the step (a) on a computer based on the simulated steps, the determined exposure dose, and the focal point in the step (c).

27. A parameter determination method as a method for determining for which region among regions on a silicon wafer a parameter in a photolithography process should be optimum when steps in the regions are different from each other, the method comprising the steps of:

holding the steps in the regions;

computing the average of the steps in the regions;

computing the variance of the steps in the regions; and

searching for an optimum parameter in the photolithography with which the number of defects is minimum based on the average of the steps in the regions and the variance of the steps in the regions.

28. The parameter determination method of claim 27, wherein the parameter in the photolithography process includes an exposure dose.

29. The parameter determination method of claim 27, wherein the parameter in the photolithography process includes a focal point.

30. The parameter determination method of claim 27, wherein the parameter in the photolithography process includes an exposure dose and a focal point.

31. A semiconductor device fabrication method, wherein a plurality of process management patterns are available in a semiconductor fabrication process, and

the process management pattern to be used is determined in advance based on the result of parameter simulation in a photolithography process.

32. The semiconductor device fabrication method of claim 31, wherein the process management pattern to be used is determined in advance based on the result of exposure dose simulation.

33. The semiconductor device fabrication method of claim 31, wherein the process management pattern to be used is determined in advance based on the result of defocus simulation.

34. The semiconductor device fabrication method of claim 31, wherein the process management pattern to be used is determined in advance based on the integrated results of step simulation, exposure dose simulation, and defocus simulation.

35. A mask pattern verification method as a verification method of extracting from a mask pattern a defect that is to cause a problem in fabrication, the mask pattern being one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern, the verification method comprising the steps of:

simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface;

holding values of the steps computed by the simulation as discrete values according to the density distribution of the semiconductor circuit pattern in the form of a table;

converting the values of the steps to size shift values of a semiconductor circuit pattern formed on a silicon wafer;

forming a semiconductor circuit pattern image from the result of the size conversion;

extracting circuit information from the semiconductor circuit pattern image; and

locating a fault point and outputting the result.

36. The mask pattern verification method of claim 35, further comprising the step of:

simulating the yield on a computer based on the simulation result of the circuit operation.

37. A mask pattern verification method as a verification method of extracting from a mask pattern a defect that is to cause a problem in fabrication, the mask pattern being one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern, the verification method comprising the steps of:

simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface;

holding values of the steps computed by the simulation as discrete values according to the density distribution of the semiconductor circuit pattern in the form of a table;

converting the values of the steps to size shift values of a semiconductor circuit pattern formed on a silicon wafer;

forming a semiconductor circuit pattern image from the result of the size conversion;

simulating a defect factor occurring with a given probability in fabrication on a computer;

simulating the yield on a computer based on the semiconductor circuit pattern image and the simulation result of the defect factor; and

locating a fault point and outputting the result.

38. A mask pattern verification method as a verification method of extracting from a mask pattern a defect that is to cause a problem in fabrication, the mask pattern being one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern, the verification method comprising the steps of:

shrinking the mask pattern uniformly to form a semiconductor circuit pattern image; and

extracting circuit information from the semiconductor circuit pattern image.

39. The mask pattern verification method of claim 38, further comprising the steps of:

simulating a defect factor occurring with a given probability in fabrication on a computer;

simulating the yield on a computer based on the semiconductor circuit pattern image and the simulation result of the defect factor; and

locating a fault point and outputting the result

40. A mask pattern verification method as a verification method of extracting from a mask pattern a defect that is to cause a problem in fabrication, the mask pattern being one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern, the verification method comprising the steps of:

simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface;

holding values of the steps computed by the simulation as discrete values according to the density distribution of the semiconductor circuit pattern in the form of a table;

converting the values of the steps to size shift values of a semiconductor circuit pattern formed on a silicon wafer;

forming a first semiconductor circuit pattern image from the result of the size conversion;

shrinking the first semiconductor circuit pattern image uniformly to form a second semiconductor circuit pattern image;

extracting circuit information from the second semiconductor circuit pattern image;

simulating circuit operation using the circuit information; and

locating a fault point and outputting the result.

41. A mask pattern verification method as a verification method of extracting from a mask pattern a defect that is to cause a problem in fabrication, the mask pattern being one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern, the verification method comprising the steps of:

simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface;

holding values of the steps computed by the simulation as discrete values according to the density distribution of the semiconductor circuit pattern in the form of a table;

converting the values of the steps to size shift values of a semiconductor circuit pattern formed on a silicon wafer;

forming a first semiconductor circuit pattern image from the result of the size conversion;

shrinking the first semiconductor circuit pattern image uniformly to form a second semiconductor circuit pattern image;

simulating a defect factor occurring with a given probability in fabrication on a computer;

simulating the yield on a computer based on the second semiconductor circuit pattern image and the simulation result of the defect factor; and

locating a fault point and outputting the result.

42. A mask pattern verification method as a verification method of extracting from a mask pattern a defect that is to cause a problem in fabrication, the mask pattern being one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern, the verification method comprising the steps of:

shrinking the mask pattern uniformly to form a semiconductor circuit pattern image;

extracting circuit information from the semiconductor circuit pattern image;

simulating circuit operation using the circuit information;

simulating the yield on a computer based on the simulation result of the circuit operation; and

locating a fault point and outputting the result.

43. A mask pattern verification method as a verification method of extracting from a mask pattern a defect that is to cause a problem in fabrication, the mask pattern being one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern, the verification method comprising the steps of:

simulating steps formed on a silicon wafer surface on a computer from a density distribution of a semiconductor circuit pattern on the silicon wafer surface;

holding values of the steps computed by the simulation as discrete values according to the density distribution of the semiconductor circuit pattern in the form of a table;

converting the values of the steps to size shift values of a semiconductor circuit pattern formed on a silicon wafer;

forming a first semiconductor circuit pattern image from the result of the size conversion;

shrinking the first semiconductor circuit pattern image uniformly to form a second semiconductor circuit pattern image;

extracting circuit information from the second semiconductor circuit pattern image;

simulating circuit operation using the circuit information;

simulating the yield on a computer based on the simulation result of the circuit operation; and

locating a fault point and outputting the result.