Strained germanium-on-insulator device structures

• US 20050205934A1
• Filed: 05/11/2005
• Published: 09/22/2005
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AmberWave Systems Corporation
• Inventors: Gurrie, Matthew T., Hammond, Richard, Fitzgerald, Eugene A., Lochtefeld, Anthony J., Langdo, Thomas A.
• Granted Patent: US 7,414,259 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/76259 with separation/delamination along a porous layer
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66916 with a PN heterojunction gate
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78687 : with a multilayer structure or superlattice structure

Abstract

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Claims

1. A structure comprising:

a substrate having a dielectric layer disposed thereon; and

a strained semiconductor layer disposed in contact with the dielectric layer,

wherein the strained semiconductor layer comprises germanium.

2. The structure of claim 1, wherein the strained semiconductor layer is compressively strained.

3. The structure of claim 1, wherein the strained semiconductor layer comprises a thin layer and the thin layer is disposed in contact with the dielectric layer.

4. The structure of claim 3, wherein the thin layer comprises silicon.

32. The structure of claim 1, wherein the strained semiconductor layer comprises approximately 100% germanium.

33. The structure of claim 1, wherein the dielectric layer comprises at least one of germanium dioxide, germanium oxynitride, and an insulator having a dielectric constant higher than that of silicon dioxide.

34. The structure of claim 1, wherein the dielectric layer comprises silicon dioxide.

35. The structure of claim 1, wherein the strained semiconductor layer is tensilely strained.

36. The structure of claim 1, further comprising:

a transistor including;

a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

37. The structure of claim 36, further comprising:

a gate dielectric layer disposed between the strained semiconductor layer and the gate.

38. The structure of claim 37, wherein the gate dielectric layer comprises silicon dioxide.

39. The structure of claim 37, wherein the gate dielectric layer comprises a high-k material with a dielectric constant higher than that of silicon dioxide.

40. The structure of claim 36, wherein the doped semiconductor comprises a material selected from the group consisting of polycrystalline silicon and polycrystalline silicon-germanium.

41. The structure of claim 36, wherein the metal comprises a material selected from the group consisting of titanium, tungsten, molybdenum, tantalum, nickel, and iridium.

42. The structure of claim 36, wherein the metal compound comprises a material selected from the group consisting of titanium nitride, titanium silicon nitride, tungsten nitride, tantalum nitride, tantalum silicide, nickel silicide, and iridium oxide.

43. The structure of claim 36, further comprising:

an overlayer disposed above the strained semiconductor layer,

wherein the overlayer induces at least a portion of the strain in the strained semiconductor layer.

44. The structure of claim 43, wherein the overlayer comprises silicon nitride.

5-31. -31. (canceled)

45. A structure comprising:

a substrate consisting essentially of a dielectric material; and

a strained semiconductor layer disposed in contact with the dielectric material,

wherein the strained semiconductor layer comprises germanium.