Semiconductor memory device and multi-chip module comprising the semiconductor memory device

• US 20050205983A1
• Filed: 05/18/2005
• Published: 09/22/2005
• Est. Priority Date: 02/19/2002
• Status: Active Grant

• Current Assignee: Tessera Advanced Technologies Inc (Adeia Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Origasa, Kenichi, Yamasaki, Yuji
• Granted Patent: US 7,072,241 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

In a semiconductor memory device composed of a semiconductor chip and overlaid to a surface of another semiconductor chip so as to connect together, a control circuit provided in the semiconductor memory device is provided with a chip connector portion having a plurality of pads. The chip connector portion is formed to have a configuration corresponding to the maximum capacity of the memory cell array provided in the semiconductor memory device, and the location and the number of the pads are invariably determined even when the memory cell array has a capacity less than the maximum capacity. The control circuit incorporating the chip connector portion is also invariably determined so as to control reading and writing data from and into the memory cell array having the maximum capacity, regardless of the capacity of the memory cell array provided.

Claims

1-4. -4. (canceled)

5. A semiconductor memory device formed of a semiconductor chip for being overlaid onto a surface of another semiconductor chip to be electrically connected therewith, comprising:

a memory cell array including a plurality of memory cell array blocks each having a plurality of memory cells, each of the memory cell array blocks having a predetermined basic capacity;

a control circuit, which is formed on the same semiconductor chip as the memory cell array is formed, for controlling reading and writing from and into the memory cells in the memory cell array;

a common chip connector portion having terminals formed on the control circuit for connecting to another semiconductor chip; and

a plurality of individually provided chip connector portions, each individually provided for each of the memory cell array blocks, each having terminals formed on each of the memory cell array blocks, all of the plurality of individually provided chip connector portions having a same configuration.

6. The semiconductor memory device according to claim 5, wherein each of the individually provided chip connector portions includes an activation controlling terminal that controls, when a refresh operation for restoring memory cell data is performed for memory cells in a corresponding memory cell array block, whether the memory cells in the corresponding memory cell array block are activated or are not activated.

7. The semiconductor memory device according to claim 6, wherein the refresh operation is an auto-refresh operation controlled by an external clock and a control terminal.

8. The semiconductor memory device according to claim 6, wherein the refresh operation is a self-refresh operation controlled by an internal clock generated internally.

9. The semiconductor memory device according to claim 5, wherein:

each of the memory cell array blocks comprises a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells; and

each of the individually-provided chip connector portions comprises an all-of the-word-lines-activating terminal for activating all the plurality of word lines in a corresponding memory cell array block when in a first electrical state.

10. The semiconductor memory device according to claim 5, wherein:

each of the memory cell array blocks comprises a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells; and

each of the individually-provided chip connector portions comprises a half-of-the-word-lines-activating terminal for selectively activating about half of the plurality of word lines in a corresponding memory cell array block when in a first electrical state.

11. The semiconductor memory device according to claim 5, wherein a ground wire is disposed in each of the individually provided chip connector portions in the same wiring layer in which the terminals of the individually provided chip connector portions are formed, the ground wire covering most of the memory cells in the corresponding memory cell array block.

14. A multi-chip module comprising:

a slave chip that is the semiconductor memory device according to claim 5;

and

a master chip having a chip connector portion in which terminals to be connected to the slave chip are formed;

wherein the terminals of the chip connector portion of the slave chip are overlaid onto the terminals of the chip connector portion of the master chip to electrically connect the terminals of the respective chips together.

12-13. -13. (canceled)