Low noise op amp

• US 20050206454A1
• Filed: 05/04/2004
• Published: 09/22/2005
• Est. Priority Date: 03/16/2004
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Wolfson Microelectronics plc
• Inventors: Pennock, John L., Richard, Patrick E.
• Granted Patent: US 7,113,042 B2
• Time in Patent Office: Days
• US Class Current: 330/277
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 3/187 in integrated circuits
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45192 Folded cascode stages

Abstract

The present invention relates amplifiers using metal oxide semiconductor based integrated circuits. The present invention is particularly but not exclusively related to audio application mixed signal chips. The present invention provides an analogue circuit for processing analogue signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the circuit stage comprising a first said transistor device having a first oxide thickness, and a second said transistor device having a second and different oxide thickness. Preferably a cascode based op amp structure is implemented.

Claims

1. An analogue circuit for processing analogue signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the circuit stage comprising a first said transistor device having a first oxide thickness, and a second said transistor device having a second and different oxide thickness.

2. A circuit according to claim 1 wherein the first transistor device is arranged in use to have an operating voltage below a predetermined level and wherein the second transistor device is arranged such that in use it is not constrained by the predetermined operating voltage level, and wherein the second oxide thickness is greater than the first oxide thickness.

3. A circuit according to claim 2 wherein the predetermined operating voltage level is 3.6V and the first oxide thickness is 70 nm.

4. A circuit according to claim 2 wherein the second transistor device forms part of a cascode transistor device circuit within said analogue circuit.

5. A circuit according to claim 4 wherein the cascode transistor device circuit is a differential folded cascode op amp circuit.

6. A circuit according to claim 5 wherein the op amp circuit further comprises input, bias, current mirror and constant current sub-circuits and wherein said first transistor device forms part of one of said op amp sub-circuits.

7. A circuit according to claim 6 further comprising a clamp circuit arranged to limit the operating voltage of said first transistor to the predetermined operating voltage level.

8. A mixed signal integrated circuit comprising an analogue circuit for processing analogue signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the circuit stage comprising a first said transistor device having a first oxide thickness, and a second said transistor device having a second and different oxide thickness.

9. A method of processing an analogue signal comprising applying the analogue signal to an analogue circuit for processing analogue signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the analogue circuit comprising a first said transistor device having a first oxide thickness, and a second said transistor device having a second and different oxide thickness, such that the analogue signal is processed by both said transistor devices.

10. A method according to claim 9 wherein the first transistor device is arranged to have an operating voltage below a predetermined level and wherein the second transistor device is arranged such that it is not constrained by the predetermined operating voltage level, and wherein the second oxide thickness is greater than the first oxide thickness.

11. A method according to claim 10 wherein the second transistor device forms part of a cascode transistor device circuit within said analogue circuit.

12. A method of producing an analogue circuit for processing analogue signals in an integrated circuit;

the method comprising providing a number of metal oxide semiconductor transistor devices arranged to implement said analogue circuit, at least a first said transistor device having a first oxide thickness, and at least a second said transistor device having a second and different oxide thickness.

13. A method according to claim 12 further comprising providing a second number of metal oxide semiconductor transistors devices arranged to implement a digital circuit.