Semiconductor integrated circuit and magnetic storage device using the same

• US 20050207228A1
• Filed: 01/07/2005
• Published: 09/22/2005
• Est. Priority Date: 03/17/2004
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamashita, Hiroki, Yagyu, Masayoshi, Yuuki, Fumio, Kawashimo, Tatsuya
• Granted Patent: US 7,046,468 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: G11B 2005/0013 of transducers, e.g. linearisation, equalisation
• CPC Class Codes: G11B 2005/3996 large or giant magnetoresistive effects [GMR], e.g. as generated in spin-valve [SV] devices
• CPC Class Codes: G11B 5/02 Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
• CPC Class Codes: G11B 5/022 H-Bridge head driver circuit, the "H" configuration allowing to inverse the current direction in the head
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

The present invention provides a semiconductor integrated circuit capable of reducing a circuit area and a magnetic storage device using the same. The circuit in the present invention is provided with a single-stage output transistor for supplying write current to a magnetic head, a current source for outputting reference current of the write current, a diode-connected NMOS transistor for converting the current to gate voltage and having a certain device size ratio to the output transistor, a regulator circuit for transmitting gate voltage of the NMOS transistor and reducing output impedance, and a CMOS circuit for setting power supply voltage to an output of the regulator circuit and controlling the gate voltage of the output transistor. Then, this circuit is applied as a write circuit in a magnetic storage device.

Claims

1. A semiconductor integrated circuit, comprising:

a single-stage output transistor provided between a power supply node or a reference potential node and an output terminal and turned on when first voltage is set to a control input terminal and turned off when second voltage is set to said control input terminal;

a current source for generating reference current of output current generated when said output transistor is turned on;

a converter circuit for generating said first voltage by converting said generated reference current; and

a voltage switch circuit for switching the voltage of said control input terminal of said output transistor to said first or second voltage.

2. The semiconductor integrated circuit according to claim 1,

wherein said converter circuit has a function to reduce output impedance caused by the generation of said first voltage.

3. The semiconductor integrated circuit according to claim 2,

wherein said voltage switch circuit is realized by a CMOS circuit.

4. The semiconductor integrated circuit according to claim 1,

wherein said converter circuit includes a diode-connected transistor having a certain device size ratio to said output transistor.

12. A magnetic storage device, comprising:

a write circuit for writing data by supplying current to a magnetic head,

wherein said write circuit includes the semiconductor integrated circuit according to claim 1.

5. A semiconductor integrated circuit, comprising:

a single-stage output transistor provided between a power supply node or a reference potential node and an output terminal;

a replica circuit including a transistor combined with said output transistor to constitute a current mirror circuit when electric conduction is provided between control input terminals, and setting output current of said output transistor;

a switch circuit for controlling conduction and non-conduction between said control input terminals and turning off said output transistor when electric conduction is not provided between said control input terminals; and

means for improving drive capability in accordance with the switching performed by said switch circuit to provide electric conduction between said control input terminals.

6. The semiconductor integrated circuit according to claim 5,

wherein said switch circuit is realized by a CMOS circuit, and

said means for improving drive capability is realized by a regulator circuit.

7. A semiconductor integrated circuit, comprising:

a current source for generating electric current;

a diode-connected first transistor connected between a power supply node or a reference potential node and said current source and generating output voltage corresponding to current of said current source to a connection node to said current source;

a regulator circuit connected to a connection node between said current source and said current-voltage converter circuit and outputting the output voltage of said first transistor with reducing output impedance thereof;

a CMOS circuit to which voltage of said power supply node or said reference potential node and output voltage of said regulator circuit are supplied and a switching signal is inputted, and outputting said output voltage of the regulator circuit as a control output signal when said switching signal represents an on state and outputting said voltage of the power supply node or the reference potential node as said control output signal when said switching signal represents an off state; and

an output transistor provided between said power supply node or said reference potential node and an output terminal and controlled by said control output signal obtained from said CMOS circuit.

8. The semiconductor integrated circuit according to claim 7,

wherein said regulator circuit is a voltage follower circuit.

9. A semiconductor integrated circuit, comprising:

a current source for generating electric current;

a diode-connected first transistor connected between a power supply node or a reference potential node and said current source and generating output voltage corresponding to the current of said current source to a connection node to said current source;

a regulator circuit connected to a connection node between said current source and said first transistor and outputting the output voltage of said first transistor with reducing output impedance thereof;

a plurality of output transistors connected to a common output terminal connected to a load; and

a plurality of CMOS circuits connected to each of control input terminals of said plurality of output transistors,

wherein voltage of said power supply node or said reference voltage terminal and output voltage of said regulator circuit are supplied to each of said CMOS circuits,

individual switching signals are inputted to said CMOS circuits,

said CMOS circuits transmit the output voltage of said regulator circuit to a control input terminal of the corresponding output transistor when said switching signal represents an on state and transmit the voltage of said power supply node or the reference potential node when said switching signal represents an off state, thereby individually controlling said corresponding output transistors.

10. A semiconductor integrated circuit, comprising:

a first bridge between a first power supply potential node and a second power supply potential node and having an intermediate node therebetween connected to a first output terminal; and

a second bridge between said first power supply potential node and said second power supply potential node and having an intermediate node therebetween connected to a second output terminal,

wherein a first branch between said intermediate node of the first bridge and said first power supply potential node includes a first output transistor of a first conductivity type and a first CMOS circuit which is connected to a gate of said first output transistor, controls ON and OFF of said first transistor, and controls output current in an on state,

a second branch between said intermediate node of the first bridge and said second power supply potential node includes a second output transistor of a second conductivity type and a second CMOS circuit which is connected to a gate of said second output transistor, controls ON and OFF of said second output transistor, and controls output current in an on state,

a third branch between said intermediate node of the second bridge and said first power supply potential node includes a third output transistor of a first conductivity type and a third CMOS circuit which is connected to a gate of said third output transistor, controls ON and OFF of said third output transistor, and controls output current in an on state,

a fourth branch between said intermediate node of the second bridge and said second power supply potential node includes a fourth output transistor of a second conductivity type and a fourth CMOS circuit which is connected to a gate of said fourth output transistor, controls ON and OFF of said fourth output transistor, and controls output current in an on state,

a first current control circuit for applying first control voltage, which defines a limit value of output current when the corresponding output transistors are in an on state, to said first CMOS circuit and said third CMOS circuit is provided, and

a second current control circuit for applying second control voltage, which defines a limit value of output current when the corresponding output transistors are in an on state, to said second CMOS circuit and said fourth CMOS circuit is provided.

11. The semiconductor integrated circuit according to claim 10,

wherein said first current control circuit includes a first current source for generating first reference current, a first current-voltage converter circuit provided between said first power supply potential node and said first current source, and a first regulator circuit for outputting the output voltage of said first current-voltage converter circuit to said first CMOS circuit and said third CMOS circuit with reducing the output impedance thereof, and

said second current control circuit includes a second current source for generating second reference current, a second current-voltage converter circuit provided between said second power supply potential node and said second current source, and a second regulator circuit for outputting the output voltage of said second current-voltage converter circuit to said second CMOS circuit and said fourth CMOS circuit with reducing the output impedance thereof.