Trench-gate semiconductor device and method of manufacturing

• US 20050208722A1
• Filed: 05/21/2003
• Published: 09/22/2005
• Est. Priority Date: 05/31/2002
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Rutter, Philip, Peake, Steven T.
• Granted Patent: US 7,232,726 B2
• Time in Patent Office: Days
• US Class Current: 438/259
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate (24) provided below the trenched gate (8) is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove (28a) into the semiconductor body (20) for receiving the gate (8), and etching a second groove (28b) into the top major surface (20a) of the semiconductor body (20), the second groove (28b) extending from the bottom of the first groove (28a) and being narrower than the first grove. The invention enables better control of the vertical extent of the gate below the top major surface (20a) of the semiconductor body.

Claims

1. A method of manufacturing a trench-gate semiconductor device, the device including a semiconductor body (20) defining a first portion (10a) of a trench having an insulated gate (8) therein, a second portion (10b) of the trench extending from the bottom of the first trench portion (10a), the semiconductor body comprising a source region (2) and a drain region (4) of a first conductivity type which are separated by a channel-accommodating region (6) adjacent to the first trench portion (10a), the drain region (4) comprising a drain drift region (4a) and a drain contact region (4b), with the drain drift region (4a) between the channel-accommodating region (6) and the drain contact region (4b), and the drain drift region doped to a lesser extent than the drain contact region, and a field plate (24) in the second portion (10b) of the trench between the gate (8) and the drain contact region (4b), the is method including the steps of:

(a) etching a first groove (28a) into the semiconductor body (20);

(b) forming spacers (34) adjacent the sidewalls of the first groove (28a) which define a window (34a) therebetween;

(c) etching a second groove (28b) into the semiconductor body (20) through the window (34a) between the spacers (34), the second groove (28b) extending from the bottom of the first groove towards the drain contact region (4b) and being narrower than the first groove (28a); and

(d) forming a field plate insulating layer (26b) by oxidising the bottom and sidewalls of the second groove (28b).

2. A method of claim 1 including the steps of:

(e) providing the field plate (24) over the field plate insulating layer (26b) in the second groove (28b) by filling the first and second grooves (28a,28b) with electrode material and etching it back until the field plate insulating layer is exposed;

(f) removing the spacers (34);

(g) forming a gate insulating layer (26a) over the field plate (24) and at the bottom and sidewalls of the first groove (28a); and

(h) providing the gate (8) over the gate insulating layer.

3. A method of claim 1 including the steps of:

(i) removing the spacers (34);

(j) forming a gate insulating layer (26a) over the bottom and sidewalls of the first groove (28a); and

then

(k) filing the first and second grooves (28a,28b) with electrode material to form the gate (8) and field plate (24).

4. A trench-gate semiconductor device manufactured according to a method of any preceding claim wherein the width of the first trench portion (10a) is greater than the width of the second trench portion (10b).

5. A trench-gate semiconductor device manufactured according to the method of claim 2 wherein the field plate (24) is connected to the source region (2).

6. A trench-gate semiconductor device manufactured according to the method of claim 2 wherein the field plate (24) is connected to a bias potential greater than the gate potential and near to the bulk breakdown voltage of the drain drift region (4a).

7. A module (60) comprising a device of claim 6 wherein the field plate (24) is connected to an internal voltage line of the module.

8. A device of claim 6 or a module of claim 7 wherein an additional external terminal (54) is provided which is electrically connected to the field plate (24).

9. A device of claim 6 or claim 7 or a module of claim 7 or claim 8 wherein the bias potential is around 60 to 100% of the bulk breakdown voltage of the drain drift region (4a).

10. A device or module of claim 9 wherein the bias potential is around 80% of the bulk breakdown voltage of the drain drift region (4a).