Semiconductor device and manufacturing method of the same

• US 20050208735A1
• Filed: 03/02/2005
• Published: 09/22/2005
• Est. Priority Date: 03/05/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Kanto Sanyo Semiconductors Company Limited (Panasonic Holdings Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Noma, Takashi, Seki, Yoshinori, Wakui, Motoaki
• Granted Patent: US 7,456,083 B2
• Time in Patent Office: Days
• US Class Current: 438/460
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

The invention is directed to an improvement of cutting accuracy in a cutting process when a semiconductor device attached with a supporting member is manufactured. The invention provides a manufacturing method of a semiconductor device where a semiconductor wafer attached with a glass substrate is cut with moving a rotation blade along a dicing region and has following features. A pair of alignment marks is formed facing each other over the dicing region on the semiconductor wafer. Then, when the rotation blade is to be aligned on a center of the dicing region, that is, on a centerline thereof in the cutting process, positions of the alignment marks are detected by a recognition camera, the centerline is calculated based on the detection result, and the rotation blade is aligned on the centerline to perform cutting.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer comprising a layer disposed on a front surface of the semiconductor wafer, a first electrode pad and a second electrode pad that are formed on the front surface, and a supporting member attached to the front surface;

forming on a back surface of the semiconductor wafer a first alignment mark and a second alignment mark;

detecting positions of the first and second alignment marks;

calculating a middle position of the positions of the first and second alignment marks;

placing a blade at the calculated middle position on a side of the semiconductor wafer corresponding to the back surface; and

cutting using the aligned blade the layer disposed on the front surface between the first and second electrode pads and along a predetermined direction so that the blade reaches the semiconductor wafer.

2. The method of claim 1, wherein the predetermined direction is a direction normal to a direction connecting the first and second alignment marks.

3. The method of claim 1, wherein the detecting is performed using a recognition camera.

4. The method of claim 1, further comprising etching the semiconductor wafer from the back surface to expose the first and second electrode pads.

5. The method of claim 1, wherein the first and second alignment marks are formed of a material used in a manufacturing process of the semiconductor device.

6. The method of claim 1, wherein the first and second alignment marks are dents formed by etching.

7. The method of claim 1, further comprising another detecting of the positions of the first and second alignment marks, another calculating of the middle position, placing a blade at the calculated middle position, and cutting the supporting member at the calculated middle position along the predetermined direction so as to form individual semiconductor dies.

8. The method of claim 7, wherein the first and second alignment marks are formed of a material used in a manufacturing process of the semiconductor device.

9. The method of claim 7, wherein the first and second alignment marks are dents formed by etching.

10. A semiconductor device comprising:

a semiconductor die;

a pad electrode disposed on a front surface of the semiconductor die;

a supporting member attached to the front surface; and

an alignment mark disposed on a back surface of the semiconductor die.

11. The semiconductor device of claim 10, wherein the alignment mark is formed of a material used in a manufacturing process of the semiconductor device.

12. The semiconductor device of claim 11, wherein the alignment mark is a dent formed by etching.