Direct conversion receiver architecture

• US 20050208916A1
• Filed: 05/16/2005
• Published: 09/22/2005
• Est. Priority Date: 02/16/2001
• Status: Active Grant

• Current Assignee: Christian Holenstein, Inyup Kang, Li Tao, Matthew L. Severson, Paul E. Peterzell
• Original Assignee: Christian Holenstein, Inyup Kang, Li Tao, Matthew L. Severson, Paul E. Peterzell
• Inventors: Kang, Inyup, Li, Tao, Peterzell, Paul E., Severson, Matthew L., Holenstein, Christian
• Granted Patent: US 8,634,790 B2
• Time in Patent Office: Days
• US Class Current: 455/245.200
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals

Abstract

A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Claims

1. A method of processing a desired signal in a wireless communication system, comprising:

amplifying the desired signal with a first gain having a coarse resolution;

downconverting the amplified signal from radio frequency (RF) to baseband with a single frequency downconversion stage;

digitizing the downconverted signal to provide samples; and

digitally amplifying the samples with a second gain having a fine resolution to provide output data having a desired signal amplitude.

2. The method of claim 1, further comprising:

correcting for DC offset in the samples with a DC loop, wherein the DC offset corrected samples are digitally amplified.

4. The direct downconversion receiver of claim 2, further comprising:

a DC offset canceller operative to correct for DC offset in the samples, and wherein the DVGA is operative to amplify the DC offset corrected samples.

5. The direct downconversion receiver of claim 2, wherein the AGC loop is further operative to provide a second gain for the RF front-end unit.

3. A direct downconversion receiver comprising:

an RF front-end unit operative to amplify, downconvert, and digitize a received signal to provide samples;

a digital variable gain amplifier (DVGA) operative to amplify the samples with a first gain to provide output data having a desired signal amplitude; and

an automatic gain control (AGC) loop operative to provide the first gain for the DVGA based in part on the output data.

6. An apparatus in a wireless communication system, comprising:

first means for amplifying a received signal;

means for canceling a DC offset in the amplified signal;

second means for digitally amplifying the DC offset cancelled signal; and

means for measuring the digitally amplified signal and to control the gains of the first and second amplifying means.

7. A receiver unit comprising:

an analog variable gain amplifier;

a DC offset canceller coupled to an output of the analog variable gain amplifier;

a digital variable gain amplifier coupled to an output of the DC offset canceller;

a gain controller adapted to measure a signal output from the digital variable gain amplifier and to control the gains of the analog and digital variable gain amplifiers; and

a serial bus interface (SBI) unit operative to provide the gain for the analog variable gain amplifier via a serial bus.

8. A receiver unit comprising:

an RF front-end unit operative to amplify, downconvert, and digitize a received signal to provide samples;

a DC loop operative to cancel DC offset in the samples;

a digital variable gain amplifier (DVGA) operative to amplify the DC offset canceled samples with a first gain to provide output data having a desired signal amplitude;

an automatic gain control (AGC) loop operative to provide the first gain for the DVGA and a second gain for the RF front-end unit based in part on the output data; and

a serial bus interface (SBI) unit operative to provide the second gain to the RF front-end unit.