Serial bus interface for direct conversion receiver

• US 20050208919A1
• Filed: 05/16/2005
• Published: 09/22/2005
• Est. Priority Date: 02/16/2001
• Status: Active Grant

• Current Assignee: Brett Walker, Li Tao, Matthew L. Severson, Paul E. Peterzell
• Original Assignee: Brett Walker, Li Tao, Matthew L. Severson, Paul E. Peterzell
• Inventors: Li, Tao, Walker, Brett, Peterzell, Paul E., Severson, Matthew L.
• Granted Patent: US 7,174,190 B2
• Time in Patent Office: Days
• US Class Current: 455/296
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H03G 3/3078 Circuits generating control signals for digitally modulated signals
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals

Abstract

A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Claims

1. A method of controlling one or more analog circuits via a serial bus, comprising:

receiving a control for a particular analog circuit;

forming a message corresponding to the received control;

sending the message over the serial bus;

receiving the message at the particular analog circuit; and

adjusting one or more characteristics of the particular analog circuit based on the received message.

2. The method of claim 1, wherein the particular analog circuit is an amplifier configurable to operate at one of a plurality of discrete gains, and wherein the message is indicative of a specific discrete gain to be used for the amplifier.

3. The method of claim 1, wherein the message is used to adjust a bias current for the particular analog circuit.

4. The method of claim 1, wherein the message is used to adjust the frequency for a signal generated by the particular analog circuit.

5. The method of claim 1, wherein each of the one or more analog circuits is assigned a respective priority, and wherein messages are sent to the one or more analog circuits based in part on their assigned priorities.

6. The method of claim 1, wherein each of the one or more analog circuits is associated with a respective address.

7. An apparatus for controlling one or more analog circuits via a serial bus, comprising:

means for receiving a control for a particular analog circuit;

means for forming a message corresponding to the received control;

means for sending the message over the serial bus;

means for receiving the message at the particular analog circuit; and

means for adjusting one or more characteristics of the particular analog circuit based on the received message.

8. A receiver unit comprising:

an RF front-end unit operative to amplify, downconvert, and digitize a received signal to provide samples;

a digital signal processor operative to process the samples to provide output data; and

a serial bus interface (SBI) unit operative to provide controls for the RF front-end unit via a serial bus.

9. The receiver unit of claim 8, wherein the SBI unit is configured to support a plurality of hardware request channels.

10. The receiver unit of claim 9, wherein each hardware request channel is associated with a respective priority.

11. The receiver unit of claim 9, wherein each hardware request channel is operable to send messages via a plurality of possible data transfer modes.

12. The receiver unit of claim 11, wherein the plurality of possible data transfer modes include a fast transfer mode and an interrupt transfer mode.