Method and system for generating test pulses to test electronic elements

• US 20050209805A1
• Filed: 09/08/2004
• Published: 09/22/2005
• Est. Priority Date: 03/19/2004
• Status: Abandoned Application

• Current Assignee: King Yuan Electronics Company Limited
• Original Assignee: King Yuan Electronics Company Limited
• Inventors: Lin, Diann-Fang, Chang, Shih-Bou
• Application Number:
  US10/935,084
• Publication Number:
  US 20050209805A1
• Time in Patent Office: Days
• US Class Current: 702/79
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence

Abstract

A method and system for generating test pulses to test electronic elements are disclosed. After determining a transmission clock, which is smaller than a test clock, and a serial of predetermined pulses, the serial of data bits corresponding to the serial of predetermined pulses can be generated. Then the serial of data bits can be transformed into a serial data stream for transmission. By transmitting the serial data stream according to the transmission clock, the serial of predetermined pulses corresponding to the test clock can be generated.

Claims

1. A method for generating test pulses to test an electronic element, comprising:

determining a transmission clock, a serial of predetermined pulses, and a test clock corresponding to the serial of predetermined pulses, wherein said serial of predetermined pulses are sent to said electronic element and the frequency of said transmission clock is higher than the frequency of said test clock;

generating a plurality of serial data bits, wherein said serial data bits are generated from said serial of predetermined pulses and said transmission clock;

transforming said serial data bits into a serial data stream; and

sending said serial data stream to said electronic element, wherein said data stream is transmitted in a specific frequency to send a specific number of bits for forming said serial of predetermined pulses according to said transmission clock.

2. The method of claim 1, wherein the frequency of said transmission clock is a multiplier of the frequency of said test clock and said transmission clock is synchronized to said test clock in the multiplier of the period.

3. The method of claim 2, wherein said serial of predetermined pulses comprises a plurality of pulses;

and each of them is generated by the corresponding bits of said serial of data bits.

4. The method of claim 3, wherein the number of the correspondent bits of said serial of data bits is said multiplier.

5. The method of claim 1, wherein a sub-pulse corresponding to a bit of said serial of data bits is generated in a period of said transmission clock;

and said sub-pulse maintains the voltage representing the logical data of correspondent bit value during said period.

6. The method of claim 1, further comprising a pre-emphasized serial data stream, wherein the voltage of said serial of predetermined pulses is regulated by pre-emphasizing before transmission.

7. The method of claim 1, wherein said serial data stream is transformed from parallel data streams;

said parallel data streams are interleaved from said serial of data bits.

8. The method of claim 7, wherein the information of said serial of data bits is interleaved to said parallel data streams in order.

9. A system for generating test pulses to test an electronic element, comprising:

a clock generator to generate a transmission clock and a test clock for an electronic element, wherein the frequency of said transmission clock being higher than the frequency of said test clock;

a storage unit to store a serial of data bits, wherein said serial of data bits being generated from a serial of predetermined pulses and said transmission clock;

a transformation unit, wherein said serial of data bits being retrieved from said storage unit and transformed into a serial data stream by said transformation unit; and

a transmission unit to transmit said serial data stream, wherein said serial of predetermined pulses being generated according to the fixed number of bits of said serial data stream in the fixed frequency of said transmission clock.

10. The system of claim 9, wherein the frequency of said transmission clock is a multiplier of the frequency of said test clock and said transmission clock is synchronized to said test clock in the multiplier of the period.

11. The system of claim 10, wherein said serial of predetermined pulses comprises a plurality of pulses;

and each of them is generated by the corresponding bits of said serial of data bits.

12. The system of claim 11, wherein the number of the correspondent bits of said serial of data bits is said multiplier.

13. The system of claim 9, wherein a sub-pulse corresponding to a bit of said serial of data bits is generated in a period of said transmission clock;

and said sub-pulse maintains the voltage representing the logical data of correspondent bit value during said period.

14. The system of claim 13, wherein the voltage representing the logical data of correspondent bit value of said sub-pulse is regulated by pre-emphasizing before transmission.

15. The system of claim 9, wherein said serial data stream is transformed from parallel data streams;

said parallel data streams are interleaved from said serial of data bits.

16. The system of claim 15, wherein the information of said serial of data bits is interleaved to said parallel data streams in order.

17. A programmable latch array with serializer for generating test pulses to test an electronic element, comprising:

an apparatus comprising a programmable latch array with a serializer for generating a test clock and a transmission clock to said electronic element and said serializer, respectively, and for storage of a serial of data bits which is generated from said transmission clock and a serial of predetermined pulses corresponding to said test clock, wherein the frequency of said transmission clock being higher than the frequency of said test clock; and

a transformation unit, wherein said serial of data bits retrieved by said transformation unit being transmitted by said serializer, and said serial of predetermined pulses being generated according to the fixed number of bits of said serial of data bits in the fixed frequency of said transmission clock.

18. A programmable latch array with serializer for generating test pulses to test an electronic element of claim 17, wherein the frequency of said transmission clock is a multiplier of the frequency of said test clock and said transmission clock is synchronized to said test clock in the multiplier of the period.

19. A programmable latch array with serializer for generating test pulses to test an electronic element of claim 18, wherein said serial of predetermined pulses comprises a plurality of pulses;

and each of them is generated by the corresponding bits of said serial of data bits.

20. A programmable latch array with serializer for generating test pulses to test an electronic element of claim 19, wherein the number of the correspondent bits of said serial of data bits is said multiplier.

21. A programmable latch array with serializer for generating test pulses to test an electronic element of claim 19, wherein a sub-pulse corresponding to a bit of said serial of data bits is generated in a period of said transmission clock;

and said sub-pulse maintains the voltage representing the logical data of correspondent bit value during said period.

22. A programmable latch array with serializer for generating test pulses to test an electronic element of claim 21, wherein the voltage representing the logical data of correspondent bit value of said sub-pulse is regulated by pre-emphasizing before transmission.