Novel process method of source drain spacer engineering to improve transistor capacitance

• US 20050212041A1
• Filed: 05/11/2005
• Published: 09/29/2005
• Est. Priority Date: 06/30/2003
• Status: Abandoned Application

• Current Assignee: Jihong Chen, Kaiping Liu, Zhiqiang Wu
• Original Assignee: Jihong Chen, Kaiping Liu, Zhiqiang Wu
• Inventors: Wu, Zhiqiang, Liu, Kaiping, Chen, Jihong
• Application Number:
  US11/127,941
• Publication Number:
  US 20050212041A1
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.

Claims

1-27. -27. (canceled)

28. A transistor comprising:

a gate structure formed over a substrate;

a source region formed within the substrate adjacent the gate structure;

a drain region formed within the substrate adjacent the gate structure;

a first compensation region formed within the substrate adjacent the gate structure and within the source region;

a second compensation region formed within the substrate adjacent the gate structure and within the drain region;

a channel underlying the gate structure and separating the source and drain regions and the first and second compensation regions, the source and drain regions being separated by a first distance and the first and second compensation regions being separated by a second distance, the first distance being greater than the second distance.

29-33. -33. (canceled)

34. A transistor, comprising:

a gate structure overlying a semiconductor body;

source and drain regions having a first depth and a first conductivity type within the semiconductor body, and defining a channel region therebetween having a second conductivity type below the gate structure;

extension regions of the first conductivity type having a second depth within the semiconductor body, and disposed between the source and drain regions and the channel, respectively;

halo regions of the second conductivity type having a third depth within the semiconductor body, and extending below the extension regions, wherein the third depth is greater than the second depth;

compensation regions of the first conductivity type having a portion disposed between the source and drain regions and their corresponding extension regions with a fourth depth, wherein the fourth depth is greater than the second depth and less than the third depth, and wherein a dopant concentration of the compensation regions is less than a dopant concentration of the source and drain regions, thereby defining a generally laterally extending junction having a first portion nearest the channel corresponding to the extension regions and halo regions, and a second portion corresponding to the compensation regions and the halo regions, respectively.

35. The transistor of claim 34, further comprising a multi-component spacer associated with sidewalls of the gate structure, the multi-component spacer comprising:

an “

L”

shaped spacer generally adjacent the sidewalls of the gate structure; and

another spacer residing on a first portion of the “

L”

shaped spacer and exposing a second portion of the “

L”

shaped spacer,

wherein the exposed portion of the “

L”

shaped spacer has a width that corresponds to a width of the second portion of the generally laterally extending junction.

36. The transistor of claim 35, wherein the “

L”

shaped spacer comprises an “

L”

shaped oxide spacer and an “

L”

shaped nitride spacer lying thereover.

37. The transistor of claim 35, wherein the “

L”

shaped spacer comprises an “

L”

shaped oxide spacer and an “

L”

shaped polysilicon spacer lying thereover, and wherein the another spacer comprises an oxide overlying a portion of the polysilicon.