Incorporation of nitrogen into high k dielectric film

• US 20050212119A1
• Filed: 05/17/2005
• Published: 09/29/2005
• Est. Priority Date: 10/02/2001
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: Christophe Pomarede, Eric J. Shero
• Inventors: Pomarede, Christophe, Shero, Eric J.
• Granted Patent: US 7,405,453 B2
• Time in Patent Office: Days
• US Class Current: 257/705
• CPC Class Codes: C23C 16/308 Oxynitrides
• CPC Class Codes: C23C 16/452 by activating reactive gas streams before their introduction into the reaction chamber, e.g. by ionisation or addition of reactive species
• CPC Class Codes: C23C 16/455 characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28017 the insulator being formed after the semiconductor body, the semiconductor being silicon
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/31683 of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
• CPC Class Codes: H01L 21/318 composed of nitrides
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/932 : Boron nitride semiconductor
• CPC Class Codes: Y10T 428/12021 : having composition or density gradient or differential porosity
• CPC Class Codes: Y10T 428/12458 : having composition, density, or hardness gradient
• CPC Class Codes: Y10T 428/31678 : Of metal

Abstract

A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.

Claims

1. A dielectric layer in an integrated circuit comprising a metal oxide throughout a thickness of the dielectric layer, the metal oxide having a dielectric constant greater than about 7, the dielectric layer comprising a lower interface having a first nitrogen concentration, a bulk portion having a second nitrogen concentration lower than the first nitrogen concentration, and an upper interface having a third nitrogen concentration higher than the second nitrogen concentration.

2. The dielectric layer of claim 1, wherein the first nitrogen is lower than the third nitrogen concentration.

3. The dielectric layer of claim 2, wherein the first nitrogen concentration is greater than about 0.1 atomic % and 10 atomic %, the second nitrogen concentration is less than about 0.1 atomic %, and the third nitrogen concentration is between about 1 atomic % and 10 atomic %.

4. The dielectric layer of claim 3, wherein the first nitrogen concentration is between about 0.1 atomic % and 1 atomic % and the third nitrogen concentration is less than about 0.01 atomic %.

5. The dielectric layer of claim 1, wherein the metal oxide comprises an oxide of a Group 4 metal.

6. The dielectric layer of claim 5, wherein the metal oxide is selected from the group consisting of ZrO₂ and HfO₂.

7. A dielectric layer in an integrated circuit comprising a lower interface, a bulk portion and an upper interface, the dielectric layer comprising zirconium oxynitride at the lower interface and at the upper interface and substantially pure zirconium oxide in the bulk portion.

8. The dielectric layer of claim 7, wherein the zirconium oxynitride comprises 0.1 atomic % to 1 atomic % nitrogen at the lower interface and 1 atomic % to 10 atomic % nitrogen at the upper interface.

9. The dielectric of claim 7, wherein the nitrogen content at the lower interface is lower than that at the upper interface.

10. The dielectric of claim 7, wherein the substantially pure zirconium oxide in the bulk portion comprises less than about 0.01 atomic % nitrogen.

11. The dielectric of claim 7, wherein the lower interface and upper interface each have a thickness between about 5 and 10 Å

.

12. The dielectric of claim 7, wherein the bulk portion has a thickness of about 20 to 30 Å

.

13. The dielectric layer of claim 7, which has a total thickness between about 20 and 60 Å

.

14. The dielectric layer of claim 7, which is a gate dielectric in an integrated circuit.

15. The dielectric layer of claim 7, wherein the first interface is a substrate interface.

16. The dielectric layer of claim 7, wherein the second interface is an interface with a gate electrode.

17. A dielectric layer comprising a graded concentration of aluminum, the dielectric comprising a lower interface having a first aluminum concentration, a bulk portion having a second aluminum concentration lower than the first aluminum concentration and an upper interface having a third aluminum concentration higher than the second aluminum concentration.

18. The dielectric layer of claim 17, which comprises zirconium oxide with a graded concentration of aluminum.

19. The dielectric layer of claim 17, which comprises hafnium oxide with a graded concentration of aluminum.

20. The dielectric layer of claim 17, which is less than 7 nm thick.

21. The dielectric layer of claim 17, which is a gate dielectric in an integrated circuit.

22. The dielectric layer of claim 17, wherein the bulk portion comprises substantially pure zirconium oxide.

23. A metal oxynitride dielectric layer, wherein the nitrogen content is about 0 in a lower bulk portion and increases to between about 1 atomic % and 10 atomic % at an upper interface.

24. The metal oxynitride dielectric layer of claim 23, wherein the upper interface is an interface with a gate electrode.

25. The metal oxynitride dielectric layer of claim 23, comprising a metal selected from the group consisting of Zr and Hf.