Method and system for low-cost and high performance power factor correction

• US 20050212501A1
• Filed: 10/25/2004
• Published: 09/29/2005
• Est. Priority Date: 10/24/2003
• Status: Active Grant

• Current Assignee: Alterlume, Inc., Joseph Durante, PF1 Incorporated, Power Factor 1
• Original Assignee: PF1 Incorporated
• Inventors: Acatrinei, Benjamin
• Granted Patent: US 7,391,630 B2
• Time in Patent Office: Days
• US Class Current: 323/283
• CPC Class Codes: G05F 1/70 Regulating power factor; Regulating reactive current or power
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 1/4208 Arrangements for improving power factor of AC input
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A Low Cost High Performances Power Factor Correction method, system and apparatus, comprising a AC power source (Vac) able to provide a low frequency supply signal, a low frequency pass filter circuit (LPF) able to protect the power source (Vac) against reverse high frequency signal noise, a rectifier circuit (BR) able to provide a fully rectify low frequency supply signal, a high frequency DC/DC converter circuit (PFC-LSC) able to convert the fully rectified low frequency supply signal into a rectified high frequency supply signal and having the capability to absorb and deliver at any moment a current amount contingent and linearly proportional in amplitude to its supply voltage amount and/or its driving pulses duty cycle ratio, a small signal controller circuit (PFC-SSC) able to control the converter circuit and a complex load circuit (CL) including at least one capacitor able to storage the rectified high frequency supply signal, so the small signal controller circuit (PFC-SSC) controls the large signal converter circuit (PFC-LSC) by means of a pulse width modulation driving signal consisting of trains of pulses constant in frequency and duty cycle during a period of time equal or longer than one of the AC power source (Vac) supply signal semi-cycle period so during each the supply signal'"'"'s semi-cycle period, as long as the controlling pulse is constant, the current amount absorbed by the large signal circuit (PFC-LSC) from the AC power source (Vac) is contingent and linearly proportional to the AC power source'"'"'s voltage amount only, so the AC power source'"'"'s output current and voltage amount follows an identical graphic shape and so the energy transfer'"'"'s power factor parameter of the AC power source (Vac) and the complex load (CL) system is improved near unity.

Claims

1. A power factor correction system for improving near unity the electrical energy transfer'"'"'s power factor parameter in a low frequency AC power source to a complex load circuit, the system comprising:

an AC power source for providing a low frequency supply signal;

a full rectifier circuit having a negative output and a positive output operatively connected to the AC power source for converting the AC power source supply signal into a low frequency fully rectified supply signal;

a high frequency controllable C/DC boost converter circuit operatively coupled to the full rectifier circuit for converting the low frequency fully rectified supply signal first into a high frequency supply signal and finally into a DC voltage output higher in amount than the low frequency fully rectified supply signal'"'"'s peak voltage amount, comprising;

a capacitive circuit coupled across the output of the rectifier circuit, properly sized for having high impedance in respect to the AC power source low frequency supply signal and low impedance with respect to the converter high frequency supply signal;

an oscillating inductor coupled at one end to the positive output of the rectifier circuit, the inductor having a charging time and a discharging time and the inductor being properly sized so that the momentary current amount across the inductor increases linearly and direct proportional with its supply voltage and/or its charging time amount, for delivering a high frequency pulse signal during its discharging time;

a controllable power switch circuit coupled at one end to the other end of the oscillating inductor the switch is coupled at the other end to the negative output of the bridge circuit for periodically charging the oscillating inductor in accordance with a high frequency driving pulse signal; and

a high frequency rectifier diode having an anode and a cathode the anode is coupled to the second end of the oscillating inductor and one end of the power switch and the cathode is connected to the DC/DC converter circuit output;

a complex load including at least one capacitive circuit able to stone the converter'"'"'s DC voltage output, the complex load having a positive end and a negative end, the positive end of the complex load being coupled to the DC/DC converter circuit'"'"'s output and the negative end of the complex load is coupled to the negative output of the full rectifier circuit; and

a high frequency controller circuit capable to provide the controllable switch with a proper driving pulse signal including trains of pulses constant in frequency and duty cycle during a time equal to or longer than one semi-cycle period of the AC power source supply signal so that the current amount absorbed by the DC/DC converter from the AC power source is contingent and linearly proportional to the AC power source supply signal voltage'"'"'s amount only, as long the DC voltage stored in the complex load'"'"'s capacitive circuit is higher in amount than the low frequency fully rectified supply signal'"'"'s peak voltage amount.

6. The systems of claims 1, 2, 3, 4, or 5 wherein:

a low frequency pass filter circuit is operatively connected between the low frequency AC power source and the full rectifier circuit for simultaneously supplying the circuit and protecting the AC power source against reverse high frequency signals.

2. A power factor correction system for improving near unity the electrical energy transfer'"'"'s power factor parameter in a low frequency AC power source to a complex load circuit, the system comprising:

an AC power source for providing a low frequency supply signal;

a low frequency pass filter circuit for protecting the power source against reverse high frequency signal noise;

a full rectifier circuit having a negative output and a positive output operatively connected to the AC power source for converting the AC power source supply signal into a low frequency fully rectified supply signal;

a high frequency controllable DC/DC buck-boost converter circuit operatively coupled to the full rectifier circuit for converting the low frequency fully rectified supply signal first into a high frequency supply signal and finally into a DC voltage output, comprising;

a capacitive circuit coupled across the output of the rectifier circuit, properly sized for having high impedance in respect to the AC power source low frequency supply signal and low impedance in respect to the converter high frequency signal;

an oscillating inductor coupled at one end to the positive output of the rectifier circuit, the inductor having a charging time and a discharging time and the inductor being properly sized so that the momentary current amount across the inductor increases linearly and in direct proportion with its supply voltage and/or its charging time amount, for delivering a high frequency pulse signal during its discharging time;

a controllable power switch circuit coupled at one end to the second end of the oscillating inductor the switch is coupled at the other end to the negative output of the bridge rectifier circuit for being able to periodically charge the oscillating inductor in accordance to a high frequency driving pulse signal; and

a high frequency rectifier diode having an anode and a cathode the anode is coupled to the second end of the oscillating inductor and one end of the power switch and the cathode is connected to the AD/DC converter circuit output;

a complex load including at least one capacitive circuit able to store the converter'"'"'s DC voltage output, the complex load having a positive end and a negative end, the positive end of the complex load being coupled to the AD/DC converter circuit output and the negative end of the complex load is coupled to the positive output of the full rectifier circuit; and

a high frequency controller circuit capable to provide the controllable switch with a proper driving pulse signal including trains of pulses constant in frequency and duty cycle during a time equal or longer than one semi-cycle period of the AC power source supply signal so that the current amount absorbed by the AC/DC converter from the AC power source is contingent and linearly proportional to the AC power source supply signal voltage'"'"'s amount only.

3. A power factor correction system for improving near unity the electrical energy transfer'"'"'s power factor parameter in a low frequency AC power source to a complex load circuit, the system comprising:

an AC power source for providing a low frequency supply signal;

a full rectifier circuit having a negative output and a positive output operatively connected to the AC power source for converting the AC power source supply signal into a low frequency fully rectified supply signal;

a complex load comprising at least one storage capacitive circuit having a positive end and a negative end, the negative end of the complex load being coupled to the negative output of the bridge rectifier;

a high frequency controllable DC/DC high efficiency snubber boost converter circuit operatively coupled to the full rectifier circuit for converting the low frequency fully rectified supply signal first into a high frequency supply signal and finally into a DC voltage output, comprising;

a first capacitive circuit coupled across the output of the rectifier bridge, properly sized for having high impedance in respect to the AC power source low frequency supply signal and low impedance in respect to the boost converter high frequency signal;

a first high frequency rectifier diode having an anode and a cathode and the cathode of the high frequency rectifier diode is coupled to the positive end of the complex load;

a second high frequency rectifier diode having an anode and a cathode and the cathode of the high frequency rectifier diode is coupled to the positive end of the complex load;

a third high frequency rectifier diode having an anode and a cathode and the anode of the high frequency rectifier diode is coupled to the positive output of the bridge rectifier;

a first oscillating inductor coupled at one end to the positive output of the bridge rectifier and at the other end to the anode of the first high frequency rectifier diode, the inductor having a charging time and a discharging time and the inductor being properly sized so that the momentary current amount across the inductor increases linearly and direct proportional with its supply voltage and/or its charging time amount, for delivering to the complex load a high frequency pulse large signal during its discharging time;

a second oscillating inductor coupled at one end to the cathode of the third high frequency rectifier diode and at the other end to the anode of the second high frequency rectifier diode, the inductor having a charging time and a discharging time and the inductor being properly sized so that the momentary current amount across the inductor increases linearly and direct proportional with its supply voltage and/or its charging time amount, for delivering to the complex load a high frequency pulse large signal during its discharging time;

a controllable power switch circuit having alternatively a ON and a OFF state coupled at one end to the first oscillating inductor and the anode of the first high frequency rectifier diode and the switch is coupled at the other end to the negative pole of the bridge rectifier for being able to periodically charge during its ON state the oscillating inductors in accordance to a high frequency driving pulse signal;

a second capacitive circuit coupled at one end to the fist inductor, the switch and the anode of the first high frequency rectifier diode and coupled at the other and to the second inductor and the second high frequency rectifier diode, properly sized for increasing the efficiency of the converter by not allowing a too fast increased of the switch'"'"'s voltage during its OFF period and the second capacitive circuit being also properly sized to do not negatively affect the high efficiency snubber converter circuit'"'"'s linearity in respect to the average current absorbed from the AC generator; and

a high frequency controller circuit capable to provide the controllable switch with a proper driving pulse signal consisting of trains of pulses constant in frequency and duty cycle during a time equal or longer than one semi-cycle period of the AC power source supply waves so that the current amount absorbed by the high efficiency snubber boost converter from the AC power source is contingent and linearly proportional to the AC power source supply signal voltage'"'"'s amount, as long as the amount of the voltage across the complex load is maintained higher than the bridge rectifier peak voltage amount.

4. A power factor correction system for improving near unity the electrical energy transfer'"'"'s power factor parameter in a low frequency AC power source to a complex load circuit, comprising:

a full rectifier circuit having a negative output and a positive output and common output operatively connected to the AC power source for converting the AC power source signal into a low frequency voltage doubler supply signal;

a three terminals complex load having a positive end, a negative end and a common end, the common end being coupled to the common output of the full rectifier circuit that is also the common connection of the power factor correction system comprising;

a first storage capacitive circuit coupled across the positive end and the common end of the three terminals complex load;

a second storage capacitive circuit coupled across the negative end and the common end of the three terminals complex load; and

a resistive circuit coupled across the positive end and the negative end of the three terminals complex load;

a controllable high frequency voltage doubler DC/DC boost converter circuit operatively coupled to the bridge rectifier and the complex load for converting the low frequency fully rectified supply signal into a DC voltage across the complex load, higher in amount than the bridge rectifier peak voltage amount for eliminating any direct current between the bridge rectifier and the complex load including;

a first capacitive circuit coupled across the positive output and the common output of the bridge rectifier, properly sized for having high impedance in respect to the AC power source low frequency supply signal and low impedance in respect to the boost converter high frequency signal;

a second capacitive circuit coupled across the negative output and the common output of the bridge rectifier, also properly sized for having high impedance in respect to the AC power source low frequency supply signal and low impedance in respect to the boost converter high frequency signal;

a first high frequency rectifier diode having an anode and a cathode and the cathode of the first high frequency rectifier diode is coupled to the positive end of the complex load;

a second high frequency rectifier diode having an anode and a cathode and the anode of the second high frequency rectifier diode is coupled to the negative end of the complex load;

a first oscillating inductor coupled at one end to the positive output of the bridge rectifier and at the other end to the anode of the first high frequency rectifier diode, the first inductor having a charging time and a discharging time and the first inductor being properly sized so that the momentary current amount across the inductor increases linearly and direct proportional with its supply voltage and/or its charging time amount, for delivering to the three terminals complex load a high frequency pulse large signal during its discharging time;

a second oscillating inductor coupled at one end to the negative output of the bridge rectifier and at the other end to the cathode of the second high frequency rectifier diode, the second inductor having a charging time and a discharging time and the second inductor being properly sized so that the momentary current amount across the second inductor increases linearly and direct proportional with its supply voltage and/or its charging time amount, for delivering to the three terminals complex load a high frequency pulse large signal during its discharging time;

a first controllable power switch circuit coupled at one end to the first oscillating inductor and the anode of the first high frequency rectifier diode and the first controllable switch is coupled at the other end to the common output of the bridge rectifier and also coupled to the common end of the three terminals load for being able to periodically charge the first oscillating inductor in accordance to a high frequency driving pulse signal;

a second controllable power switch circuit coupled at one end to the second oscillating inductor and the cathode of the second high frequency rectifier diode and the second controllable switch is coupled at the other end to the common output of the bridge rectifier and also coupled to the common end of the three terminals load for being able to periodically charge the second oscillating inductor in accordance to a high frequency driving pulse signal; and

a high frequency driving transformer comprising;

a primary coil able to directly receive and transfer simultaneously via magnetic field a pulse width modulation driving pulse signal to the first and second controllable switches;

a first secondary coil operatively connected to the first controllable switch; and

a second secondary coil operatively connected to the second controllable switch; and

a high frequency controller circuit operatively connected to the primarily coil of the high frequency driving transformer capable to provide the controllable switch with a proper driving pulse signal consisting of trains of pulses constant in frequency and duty cycle during a time equal or longer than one semi-cycle period of the AC power source supply waves so that the current amount absorbed by each of the voltage doubler boost converter circuits from the AC power source is contingent and linearly proportional to the AC power source supply signal voltage'"'"'s amount only, as long as the amount of the voltage across the complex load is maintained higher than the bridge rectifier peak voltage amount.

5. A power factor correction system for improving near unity the electrical energy transfer'"'"'s power factor parameter in a low frequency AC power source to a complex load circuit, the system comprising:

an AC power source for providing a low frequency supply signal;

a full rectifier circuit having a negative output and a positive output operatively connected to the AC power source for converting the AC power source supply signal into a low frequency fully rectified supply signal;

a high frequency controllable DC/DC converter circuit operatively coupled to the full rectifier circuit for converting the low frequency fully rectified supply signal first into a high frequency supply signal and next into a DC voltage output, comprising;

a capacitive circuit coupled across the output of the rectifier bridge, properly sized for having high impedance in respect to the AC power source low frequency supply signal and low impedance in respect to the converter high frequency signal;

an oscillating inductor coupled at one end to the positive output of the bridge rectifier the inductor having a charging time and a discharging time and the inductor being properly sized so that the momentary current amount across the inductor increases linearly and direct proportional with its supply voltage and/or its charging time amount, for delivering a high frequency pulse signal during its discharging time;

a controllable power switch circuit coupled at one end to the second end of the oscillating inductor the switch is coupled at the other end to the negative output of the bridge rectifier for being able to periodically charge the oscillating inductor in accordance to a high frequency driving pulse signal; and

a high frequency rectifier diode having an anode and a cathode the anode is coupled to the second end of the inductor and one end of the power switch and the cathode is connected to the DC/DC converter circuit output;

a complex load including at least one capacitive circuit able to storage the converter'"'"'s DC voltage output, the complex load having a positive end and a negative end, the positive end of the complex load being coupled to the DC/DC converter circuit output and the negative end of the complex load is coupled to the negative output of the full rectifier circuit when the DC/DC converter has a boost configuration or the negative end of the complex load is coupled to the positive output of the full rectifier circuit when the DC/DC converter has a buck-boost configuration; and

a high frequency controller circuit capable to provide the controllable switch with a proper driving pulse signal consisting of trains of pulses constant in frequency and duty cycle during a time equal or longer than one semi-cycle period of the AC power source supply signal so that the current amount absorbed by the DC/DC converter from the AC power source is contingent and linearly proportional to the AC power source supply signal voltage'"'"'s amount only.

7. A start enforcer system for securing the “

high input voltage/large impedance load”

worse case self supply start triggering process status of a power management controller circuit that drives a converter circuit, the controller circuit receiving initially its minimum supply voltage from an off-line voltage source until the controller circuit is able to provide itself a strong enough signal for maintaining in a safe range its supply voltage and the controller circuit having the self supply start triggering process reliant simultaneously on several internal and/or external sub-circuits behavior such as;

a resistive circuit properly and efficiently sized for providing the required minimum supply voltage to the controller circuit when the off-line voltage source reaches its minimum amount and/or the resistive circuit is properly and efficiently sized for not damaging the controller circuit when the off-line voltage source reaches its maximum voltage amount, operatively coupled to the controller circuit'"'"'s supply electrode;

a capacitive circuit properly sized for maintaining the controller circuit'"'"'s supply voltage within the controller circuit'"'"'s required range despite large variations of the controller'"'"'s output signal'"'"'s duty cycle, operatively connected across the controller'"'"'s supply electrodes;

an under voltage lockout with hysteresis sub-circuit requiring a minimum supply voltage for allowing the controller circuit to start delivering a square wave output signal and also the under voltage lockout with hysteresis sub-circuit being able to shut down the controller circuit'"'"'s output when the controller circuit'"'"'s supply voltage is lower than a pre-established voltage amount;

a voltage error amplifier feedback sub-circuit having a feedback input operatively connected to the converter circuit'"'"'s output, the converter circuit'"'"'s output voltage amount increasing initially in a direct proportional ratio to the off-line source voltage amount and the voltage error amplifier feedback sub-circuit being capable to decrees the controller output signal duty cycle ratio when the converter circuit'"'"'s output voltage reaches high amounts;

a compensation capacitor circuit operatively connected between the voltage error amplifier output and feedback input, for allowing the voltage error amplifier feedback sub-circuit amplify the feedback input'"'"'s average voltage only;

a switching voltage source sub-circuit having a low impedance output and being able to provide a near zero voltage level in respect to the feedback input'"'"'s voltage amount during the time when the under voltage lockout with hysteresis sub-circuit do not allows the controller circuit to deliver its output signal and the low impedance output being also able to provide a voltage higher in amount than the feedback input'"'"'s maximum voltage when the voltage lockout with hysteresis sub-circuit allows the controller circuit to start delivering the square wave output signal; and

a large impedance load allowing high voltage across the converter circuit'"'"'s output, the high voltage amount across the converter circuit'"'"'s output forcing the controller circuit, via the voltage error amplifier feedback sub-circuit and the compensation capacitor circuit, to decrease and maintain the output signal duty cycle ratio down to a value that is not strong enough for maintaining in a safe range the supply voltage of the controller circuit;

the system comprising;

a semiconductor diode having a pre-established threshold voltage across its terminals, operatively connected into the circuit of the voltage error amplifier sub-circuit'"'"'s feedback input and the switching voltage source sub-circuit'"'"'s low impedance output, for decreasing for a short period of time the voltage error amplifier sub-circuit'"'"'s feedback input'"'"'s voltage amount during the time when the under voltage lockout with hysteresis sub-circuit does not allows the controller circuit to start delivering an output signal and the semiconductor diode having very large impedance in a reverse position when the switching voltage source sub-circuit switches its status from near zero voltage level up to a voltage higher in amount than the feedback input'"'"'s maximum voltage; and

a resistive circuit properly sized and operatively coupled in series with the semiconductor diode for setting a precise maximum voltage amount at the voltage error amplifier'"'"'s feedback input during the time when the under voltage lockout with hysteresis sub-circuit does not allows the controller circuit to deliver its output signal, for securing, together with the semiconductor diode, a large enough duty cycle ratio output signal and/or a strong enough output signal capable to maintain the controller circuit in a safe supply voltage range as soon as the under voltage lockout with hysteresis sub-circuit allows the controller circuit to deliver its output signal.

8. The systems of claims 7 further comprising:

one or more semiconductor diodes having a pre-established threshold voltage, operatively connected into the circuit of the voltage error amplifier feedback sub-circuit'"'"'s feedback input and the switching voltage source sub-circuit'"'"'s low impedance output for decreasing the voltage error amplifier feedback sub-circuit'"'"'s feedback input'"'"'s voltage amount during the time when the under voltage lockout with hysteresis sub-circuit does not allows the controller circuit to start delivering an output signal and the two or more semiconductor diodes having very large impedance in a reverse position when the switching voltage source sub-circuit switches its status from near zero voltage level up to a voltage higher in amount than the feedback input'"'"'s maximum voltage, for securing a large enough duty cycle ratio output signal and/or a strong enough output signal capable to maintain the controller circuit in a safe supply voltage range as soon as the under voltage lockout with hysteresis sub-circuit allows the controller circuit to deliver its output signal.

9. The systems of claims 7 comprising:

a voltage limiting circuit including a group of devices such as diodes and/or zener diodes and/or reference voltage sources and/or operational amplifiers, operatively connected into the circuit of the voltage error amplifier feedback sub-circuit'"'"'s input and the switching voltage source sub-circuit'"'"'s low impedance output for decreasing the voltage error amplifier feedback sub-circuit'"'"'s feedback input'"'"'s voltage amount during the time when the under voltage lockout with hysteresis sub-circuit does not allows the controller circuit to start delivering an output signal and the voltage limiting circuit having very large impedance in a reverse position when the switching voltage source sub-circuit switches its status from near zero voltage level up to a voltage higher in amount than the feedback input'"'"'s maximum voltage, for securing a large enough duty cycle ratio output signal and/or a strong enough output signal capable to maintain the controller circuit in a safe supply voltage range as soon as the under voltage lockout with hysteresis sub-circuit allows the controller circuit to deliver its output signal.

10. A pulse width modulation controller system for driving a power factor correction converter circuit including at least three devices such as a controllable power switch, an oscillating inductor and a high frequency rectifier diode, the oscillating inductor having a charging time and a discharging time and the oscillating inductor being properly sized so that the momentary current amount of the inductor increases linearly and direct proportional with its supply voltage and/or its the charging time amount, the converter circuit being supply by a low frequency AC power source that provided a supply signal having cycles and semi-cycles via a bridge rectifier circuit having at least a positive output and a negative output and the converter circuit delivering a rectified high frequency supply signal to a complex load circuit, the complex load comprising at least one storing capacitive circuit and the controller system being capable to provide the converter circuit with a pulse width modulation driving signal consisting of trains of pulses constant in frequency and duty cycle during a period of time equal or longer than one of the AC power source supply signal semi-cycle period, comprising:

eight in/out electrodes including;

a positive voltage input supply electrode operatively connected to a DC supply voltage source placed externally to the controller system, the DC supply voltage source being a classic power supply providing a stabilized and properly sized voltage amount or the DC supply voltage source being a self supply voltage source that provides a voltage amount proportional to the controller system'"'"'s pulse width modulation driving signal'"'"'s duty cycle ratio and the DC supply voltage source comprising a properly sized large value filtrating capacitor able to reasonably stabilize the supply voltage delivered to the positive voltage input supply electrode, after the large value filtrating capacitor is fully charged;

a negative voltage or common supply electrode operatively connected to the DC voltage source;

a soft start electrode operatively connected, in respect to the common supply electrode, to a capacitive circuit placed externally to the controller system;

a driving electrode operatively connected to the power switch, for delivering the controller system'"'"'s pulse width modulation driving signal;

a current sensing electrode operatively connected to the power switch for sensing the momentary current amount of the power switch and/or for sensing the momentary current amount of other circuits;

a feedback electrode having a maximum feedback voltage threshold operatively connected to the complex load and/or other circuits, for sensing an error signal proportional to the momentary voltage amount across the load and/or across other circuits;

a compensation electrode for allowing the attachment of frequency compensation circuitries comprising at least a properly sized compensation capacitive circuit placed externally to the controller system operatively connected to the feedback electrode for securing the delivery of the trains of pulses constant in frequency and duty cycle during a period of time equal or longer than one of the AC power source supply signal semi-cycle period, the compensation electrode also allowing external adjustments and/or limitations of the controller system'"'"'s pulse width modulation driving signal'"'"'s duty cycle ratio;

a non linearity correction electrode operatively connected, to the bridge rectifier circuit'"'"'s output, for sensing the momentarily amount of the converter circuit'"'"'s input supply voltage;

the controller system comprising thirteen sub-circuits such as;

an internal supply and protection sub-circuit coupled to the positive input supply electrode operatively coupled with other controller system'"'"'s sub-circuits for providing to the controller system with all standard over voltage and/or under voltage lockout with hysteresis circuitry that shuts down the pulse width modulation driving signal when the external DC supply voltage source provides a voltage amount higher or lower than a pre-established range;

a driver sub-circuit having an input and an output for amplifying, buffering and delivering the controller system'"'"'s pulse width modulation signal to the power switch via the driving electrode, the driver sub-circuit receiving its supply voltage directly from the positive voltage input supply electrode or the driver circuit receiving its supply voltage via the internal supply and protection sub-circuit;

a voltage references sub-circuit receiving its supply voltage directly from the positive voltage input supply electrode or the voltage references circuit receiving its supply voltage via the internal supply and protection sub-circuit, for providing to the controller as more as needed precise reference voltage sources and the voltage references sub-circuit comprising at least one low impedance output switching voltage source able to provide a near zero voltage level in respect to the feedback input'"'"'s voltage amount during the time when the under voltage lockout with hysteresis sub-circuit does not allows the controller circuit to output its driving signal and the low impedance output switching voltage source being also able to provide a voltage higher in amount than the feedback input'"'"'s maximum voltage threshold when the voltage lockout with hysteresis sub-circuit allows the controller system to output its the driving signal;

a fixed frequency oscillator circuit having a set logic output, a reset logic output, a clock logic output and a voltage ramp input/output terminal, for providing synchronized square and voltage ramp signals, the voltage ramp signals comprising waves having rising periods and decaying periods;

a current limiter sub-circuit having an inverting input a non-inverting input and a logic output, the inverting input being operatively connected to one reference voltage source of the voltage references sub-circuit and the non-inverting input being coupled to the current sensing electrode, for the current limiter sub-circuit to reverse its output logic status, when the current amount sensed at the current sensing electrode is higher than a pre-established amount;

a pulse width modulation logic sub-circuit capable to generate a pulse width modulation signal comprising;

a logic output operatively connected to the driver sub-circuit input for amplifying or buffering the pulse width modulation signal;

a first shut down logic input operatively coupled to the internal supply and protection sub-circuit for shutting down the pulse with modulation signal when the external DC voltage source provides a voltage amount higher or lower than a pre-established range;

a second shut down logic input operatively connected to the current limiter sub-circuit'"'"'s logic output for shutting down the pulse with modulation signal when the current amount sensed at the current sensing electrode is higher than a pre-established amount;

a reset logic input, for terminating each the driving pulse;

a set logic input operatively connected to the oscillator'"'"'s set output, for validating the inception of each the driving pulse and the reset logic input must be already in its inactive and/or zero logic state when the set logic input is active and/or zero logic, for allowing the next and only one driving pulse during one the oscillator'"'"'s complete cycle;

a voltage error amplifier sub-circuit having an inverting input, a non-inverting input and a sink only analogic output, the sink only analogic output being coupled to the compensation electrode, the non-inverting input being operatively connected to one reference voltage source of the voltage references sub-circuit, and the inverting input being coupled to the feedback electrode, for amplifying the error signal collected at the feedback electrode, so that the controller system'"'"'s pulse width modulation driving signal'"'"'s duty cycle to be contingent and direct proportional to the momentary voltage amount reached at the compensation electrode;

a voltage limiter sub-circuit having an input and an output, comprising;

a constant current source operatively coupled between the low impedance output switching voltage reference source and the compensation electrode for simultaneously supplying the voltage error amplifier'"'"'s sink only output and also for allowing parallel voltage adjustments of other circuits placed externally to the controller system;

a zener diode operatively connected across the voltage limiter sub-circuit'"'"'s output, for limiting at a pre-established maximum voltage amount the voltage limiter sub-circuit'"'"'s output signal, so that the pre-established maximum voltage amount clamped at the output of the voltage limiter sub-circuit'"'"'s output to determine the maximum duty cycle ratio of the controller system'"'"'s pulse width modulation driving signal; and

a current limitation circuitry comprising diodes and resistive circuits operatively coupled between the input and the output terminals of the voltage limiter sub-circuit, for reducing the noise and optimizing the in/out signal transfer;

an analog reset voltage ramp driver sub-circuit comprising;

a voltage ramp buffer circuit for amplifying, under large input impedance, the current of the oscillators sub circuit'"'"'s voltage ramp signal; and

an analog reset switching system operatively connected to the clock logic output of the oscillator sub-circuit for decreasing rapidly near zero the voltage ramp signal'"'"'s voltage amount, outputted by the buffer circuit, during each time during the voltage ramp signal reaches is decaying period;

a pulse width modulation comparator sub-circuit having an inverting input, a non-inverting input and a logic output, the logic output being coupled to the reset input of the pulse width modulation logic sub-circuit, the inverting input being operatively connected to the output of the voltage limiter sub-circuit and the non-inverting input being coupled to the output of the analog reset voltage ramp driver sub-circuit, for resting periodically the pulse width modulation logic sub-circuit, so that the controller system'"'"'s pulse width modulation driving signal'"'"'s duty cycle to be contingent and direct proportional to the momentary voltage amount outputted by the voltage limiter sub-circuit in respect to the to the momentary voltage amount delivered by the analog reset voltage ramp driver sub-circuit'"'"'s output and also for the pulse width modulation comparator sub-circuit to be reset and/or forced to commute fast to zero its logic output status, each time during the voltage ramp signal reaches is decaying period, the decaying period lasting for at least as long time as a reasonable low cost comparator circuit needs for its output'"'"'s high/low commutation'"'"'s transit period;

a soft start sub-circuit having soft start input, a commutation input and a soft start output, the soft start output being coupled to the compensation electrode, the commutation input being operatively connected to the low impedance output switching voltage reference source and the soft start input being coupled via the soft start electrode to a soft start capacitive circuit placed externally to the controller system, the soft start capacitive circuit being properly sized and operatively connected to the soft start electrode with respect to the common supply electrode for forcing a smooth increase of the soft start electrodes voltage amount, the soft start sub-circuit comprising a classic one transistor, one resistor, one diode circuitry for forcing the signal'"'"'s voltage at the compensation electrode to increase as smooth as the soft start electrode signal'"'"'s voltage, so that the pulse width modulation driving signal'"'"'s duty cycle ratio to increase smooth and safe;

a start enforcer sub-circuit, having an input coupled to the low impedance output switching voltage reference source and an output coupled to the feedback input, for securing the worse self supply start triggering process case when initially the controller system is not able to provide a driving signal having a duty cycle ratio large enough for maintaining in a safe range its the DC supply voltage amount and the internal supply and protection sub-circuit shuts down the controller system'"'"'s driving signal when the DC supply voltage amount is lower than a pre-established range comprising;

a semiconductor diodes accepting a pre-established threshold voltage across its terminals, operatively connected into the circuit of the voltage error amplifier sub-circuit'"'"'s feedback input and the switching voltage source sub-circuit'"'"'s low impedance output, for decreasing the voltage error amplifier sub-circuit'"'"'s feedback input'"'"'s voltage amount and implicitly increasing the driving pulse signal duty cycle ratio until the large value filtrating capacitor is fully charged and able to reasonably stabilize the supply voltage delivered to the positive voltage input supply electrode despite large variations of the driving pulses signal duty cycle and the semiconductor diode having very large impedance in a reverse current circuit, for releasing the feedback electrode of any voltage limitation when the switching voltage source sub-circuit switches its status from near zero voltage level up to a voltage higher in amount than the maximum feedback voltage threshold amount; and

a resistive circuit properly sized and operatively coupled in series with the semiconductor diode for setting a precise start enforcing voltage amount at the feedback electrode; and

a non linearity correction sub-circuit for correcting the controller system'"'"'s driving signal'"'"'s duty cycle ratio in critical situations when the converter circuit'"'"'s input supply voltage momentary amount exceeds half of the voltage amount across the load, the non linearity correction sub-circuit having an inverting input, a non-inverting input and a sink only analogic output, the sink only analogic output being coupled to the compensation electrode, the non-inverting input being operatively connected to the feedback electrode, and the inverting input being coupled to the non linearity correction electrode, for amplifying, in respect to a variable reference voltage which is actually the momentary voltage amount of the feedback electrode, a pre-established fraction of the converter circuit'"'"'s input supply voltage, so that the controller system'"'"'s pulse width modulation driving signal'"'"'s duty cycle ratio to be reduced only when/if the momentary amount of the converter circuit'"'"'s input supply voltage reaches high values that exceed half of the voltage amount across the load and/or the controller system'"'"'s pulse width modulation driving signal'"'"'s duty cycle ratio to be reduced down to zero in the most critical boost converter'"'"'s situation when the converter circuit'"'"'s input supply voltage momentary amount reaches or exceeds the voltage amount across the load.

11. The controller systems of claim 10 comprising a number of fourteen electrodes that includes, besides the eight electrodes, another six electrodes, comprising:

a voltage reference electrode coupled to the voltage reference sub-circuit'"'"'s low impedance output switching voltage source for providing high precision reference voltage and/or switching operations circuitry to other circuits placed externally to the controller system;

an oscillator input/output electrode coupled to the fixed frequency oscillator sub-circuit'"'"'s voltage ramp i/o terminal for allowing a full control of the oscillator sub-circuit'"'"'s main parameters by the means of other circuits placed externally to the controller system;

a current sensing electrode coupled to one of the pulse width modulation comparator sub-circuit'"'"'s input for allowing the control of the output driving signal duty cycle ratio by the means of other circuits placed externally to the controller system;

a synchronization electrode operatively coupled to one of the fixed frequency oscillator sub-circuit'"'"'s terminals and/or one of the pulse width modulation sub-circuit'"'"' terminals for allowing in/out synchronization circuitry between the controller system and other circuits placed externally to the controller system;

a shut down/protection electrode operatively coupled to one of the pulse width modulation logic sub-circuit'"'"' terminals for allowing shut/down protection circuitry between the controller system and other circuits placed externally to the controller system; and

a second driving electrode operatively connected to the power switch, for delivering a second driving signal that can be similar or in opposite phase in respect to the driving electrode'"'"'s signal, so that the controller system to be able to drive simultaneously two circuits such as the controllable power switch.

12. The controller systems of claims 10 comprising externally any combinations and/or arrangements of three to fourteen electrodes and internally any combination and/or arrangements of at least three from the total of thirteen functional blocks, including at least one Analog Reset circuit and/or a Start Enforcer circuit and/or a Non Linearity Correction circuit.

13. The controller systems of claim 10 wherein which one or all amplifiers and or comparators sub-circuits may have their inverting and non-inverting inputs connected opposite way, in order to respect the logic of a specific architecture of the pulse width modulation sub-circuit and or the oscillator sub-circuit.

14. The controller systems of claim 10 wherein which:

the current limitation electrode is coupled to the pulse width modulation comparator sub circuit'"'"'s positive and/or current reading input.

15. The controller systems of claim 10 wherein which:

the non linearity correction sub-circuit delivers a signal in phase with the converter circuit'"'"'s input supply voltage and the non linearity correction sub-circuit'"'"'s output is coupled to the pulse width modulation comparator sub circuit'"'"'s positive and/or current reading input.

16. The controller systems of claim 10 wherein which:

the analog reset voltage ramp driver sub-circuit includes;

a voltage ramp buffer circuit for amplifying, under large input impedance, the current of the oscillators sub circuit'"'"'s voltage ramp signal; and

an analog reset switching circuitry, placed externally to the voltage ramp buffer circuit, the analog reset switching circuitry is operatively connected to the oscillator sub-circuit and or the pulse width modulation logic sub-circuit, for decreasing rapidly near zero the voltage ramp signal'"'"'s voltage amount, inputted by the pulse width modulation comparator sub-circuit, each time during the voltage ramp signal reaches is decaying period, so that the pulse width modulation comparator sub-circuit'"'"'s output to be reset fast back to its initial logic state.

17. The controller systems of claim 10 wherein which:

the pulse width modulation comparator sub-circuit is replaced by an analog reset comparator sub-circuit; and

the pulse width modulation logic sub-circuit is replaced by an analog reset pulse width modulation logic sub-circuit, for

the pulse width modulation comparator sub-circuit'"'"'s output to be reset fast back to its initial logic state, each time during the voltage ramp signal reaches is decaying period.

18. The controller systems of claim 10 in which the pulse width modulation controller system has eight in/out electrodes such as:

a negative voltage or common supply electrode;

a positive voltage input supply electrode that is able to perform also as a protection electrode;

a driver electrode for outputting a pulse width modulation controlling signal;

a feedback electrode for controlling the output signal'"'"'s duty cycle ratio able to accept the attachment of a start enforcer circuit;

a compensation electrode that allows external compensation of the feedback control circuits and also allows for a direct control of the output driving signal and or an internal soft start circuit;

a current sensing electrode that could be used also as a Non Linearity Correction or Maximum Duty Cycle pre-setting electrode and or as a Analog Reset electrode;

a voltage reference output electrode for supplying external circuits, able to perform also as a protection and/or switching electrode; and

an oscillator controlling electrode able to perform also as a synchronization electrode.

19. A non linearity correction system for improving the shape of the current absorbed by a controllable converter circuit from an AC power source, by means of reducing periodically the duty cycle ratio of the driving signal provided by a pulse width modulation controller circuit having a feedback input, a compensation input and a driving output to the controllable converter circuit during the time when the AC power source'"'"'s momentarily voltage amount is higher than a pre-established amount, comprising:

a sink only output operational amplifier having its output coupled to the compensation input of the controller circuit for reducing periodically the duty cycle ratio of the driving signal;

a classic two resistors and one capacitor fix gain and compensation circuit for the amplifier;

a non linearity correction reference input that is coupled to a fix reference voltage or the non linearity correction reference input is coupled to the feedback input of the controller circuit for setting the voltage threshold from where the operational amplifier starts correcting the driving signal; and

a non linearity correction input controlling in opposite phase the operational amplifier'"'"'s output, the non linearity correction input is operatively connected to the AC power source for sensing the power source voltage amount and for progressively reducing the duty cycle ratio of the driving signal in respect to the non linearity correction reference input'"'"'s voltage amount.

20. A non linearity correction system of claim 19 wherein the duty cycle ratio of the driving signal is periodically reduced using the controller'"'"'s internal error amplifier by the means of resistive circuits operatively connected from the AC power source to the controller'"'"'s feedback and compensation inputs external circuit.

21. A non linearity correction system of claim 19 wherein the controller circuit has also a current sense input and the duty cycle ratio is periodically reduced by the means of resistive circuits operatively connected from the AC power source to the controller'"'"'s current sense input'"'"'s external circuit.

22. An analog reset system for improving the performances of mixed signal circuits and for achieving a smooth control of shorter output pulses from voltage mode pulse width modulators wherein the analog comparators commutation speed is lower than the logic gates speed, comprising:

a classic mixed signal oscillator circuit comprising two comparators a flip-flop and a charge/discharge circuitry that is able to provide three synchronized output signals including;

a voltage ramp output signal having an ascendant period and a descendent period;

a square wave output Clock signal comprising pulses that last only during the ascendant period of the voltage ramp signal; and

a square wave output Set signal comprising pulses that last only during the descendant period of the voltage ramp signal;

a voltage ramp driver circuit operatively connected to the oscillator circuit for buffering the voltage ramp signal and the voltage ramp driver circuit operatively coupled to the oscillator'"'"'s Clock signal output for reducing near zero the amplitude of the voltage ramp signal during its descendent period;

a comparator circuit having its inputs operatively connected to the voltage ramp driver circuit and a variable voltage source for a smoothly control of its output signal duty cycle ratio and also for the comparator to have enough time to reset its output back to its initial logic state during the time when the voltage ramp driver keeps near zero the amplitude of the voltage ramp signal; and

a classic three NOR gates pulse with modulation logic circuit operatively connected to the comparator'"'"'s output and the pulse width modulation logic circuit being also operatively connected with the set output of the oscillator for securing not more than one output pulse per each the voltage ramp signal cycle.

23. The analog reset system of claim 22 wherein the set output signal rests directly the comparator and the voltage ramp driver circuit is a buffer.

24. The analog reset system of claim 22 wherein the comparator receives the reset signal from the pulse width modulation circuit and the voltage ramp driver circuit is a buffer.

25. The analog reset system of claim 22 wherein the comparator receives a modified voltage ramp signal having its amplitude near zero during its sad descendent period, directly from the oscillator eliminating the need of a voltage ramp driver circuit and/or synchronized square wave signal.

26. The analog reset system of claim 22 wherein a hybrid circuit including:

a classic current mode pulse width modulation controller, such as UC384, is capable of providing the oscillator, comparator and pulse width modulation circuits; and

an external discrete parts circuit provides the voltage ramp driver and the comparator reset synchronization circuitry.

27. A method of constant pulse proportional current mode of operations for a power factor correction system that improves near unity the electrical energy transfer'"'"'s power factor parameter in a low frequency AC power source to a complex load circuit, the system including a low frequency AC power source, a full rectifier circuit, a controllable high frequency DC/DC converter, a complex load including at least a storing capacitor circuit and high frequency pulse width modulation controller circuit, comprising:

rectifying the low frequency AC power source signal using a full rectifier circuit that provides a fully rectified supply signal;

converting the fully rectified signal using the high frequency controllable DC/DC converter into a rectified high frequency supply signal;

storing electrical using the storage capacitor of the complex load;

eliminating the direct current between the full rectifier circuit and the complex load using either an appropriated converter topography such as buck boost or a high frequency supply signal strong enough for keeping the DC voltage across the complex load higher in amount then the AC power source peak voltage; and

controlling the DC/DC converter with a proper driving pulse signal consisting of trains of pulses constant in frequency and duty cycle during a time equal or longer than one semi-cycle period of the AC power source supply signal so that the current amount absorbed by the DC/DC converter from the AC power source is contingent and linearly proportional to the AC power source supply signal voltage'"'"'s amount only.

28. The method of claim 27 wherein a low frequency pass filter circuit is operatively connected between the low frequency AC power source and the full rectifier circuit for simultaneously supplying the circuit and protecting the AC power source against reverse high frequency signals.

29. The method of claim 27 wherein keeping constant the main parameters of the high frequency controlling signal such as amplitude, frequency and duty cycle the power factor is greater than 0.999, the THD is lower than 1% and the efficiency of the entire system is over 95%.

30. A method of analog reset for improving the performances of mixed signal circuits and for achieving a smooth control of shorter output pulses from voltage mode pulse width modulators wherein the analog comparators commutation speed is lower than the logic gates speed, system including a classic mixed signal oscillator circuit having an ascendant period and a descendent period, a voltage ramp driving circuit, a pulse width modulation comparator circuit and a pulse width modulation logic circuit, comprising:

generating a voltage ramp signal and at least one synchronized square wave signal using the classic mixed signal oscillator;

buffering the voltage ramp signal using the voltage ramp driving circuit;

comparing the voltage ramp signal with a reference voltage and outputting a variable duty cycle square wave using a comparator circuit;

securing not more than one output pulse per voltage ramp signal'"'"'s cycle using a typical three NOR gate pulse with modulation logic circuit; and

resetting the pulse width modulation comparators output logic state during each of the voltage ramp signal'"'"'s cycle using a synchronized signal incoming from the oscillator circuit or pulse width modulation circuit.

31. The method of claim 30 wherein the comparator receives a modified voltage ramp signal having its amplitude near zero during its said descendent period, directly from the oscillator eliminating the need of a voltage ramp driver circuit and/or synchronized square wave signal.

32. A method of non linearity correction for improving the shape of the current absorbed by a controllable converter circuit from an AC power source, by means of reducing periodically the duty cycle ratio of the driving signal provided by a pulse width modulation controller circuit having a operational amplifier including a feedback input a reference input and a compensation output operatively connected for decreasing the duty cycle ratio of a driving output that provides a pulse width modulation signal to the controllable converter circuit during the time when the AC power source'"'"'s momentarily voltage amount is higher than a pre-established amount, comprising:

sensing the AC power source'"'"'s supply signal using a resistive divider circuit connected to one input of a operational amplifier;

comparing aid AC power source'"'"'s supply signal amount to a reference voltage coupled to the other input of the operational amplifier; and

decreasing periodically the duty cycle ratio of the driving output signal only when the AC power source'"'"'s supply signal amount is higher that a pre-established reference using a proper gain and compensation circuit for the operational amplifier.

33. A method of start enforcement for securing the “

high input voltage/large impedance load”

worse case self supply start triggering process status of a power management controller circuit that drives a converter circuit, the controller circuit receiving initially its minimum supply voltage from an off-line voltage source until the controller circuit is able to provide itself a strong enough signal for maintaining in a safe range its supply voltage, comprising;

keeping the feedback input of the controller circuit at a pre-established safe voltage amount before the controller start supplying itself using at least one switch and resistive circuits for allowing a large enough start up output driving pulse; and

releasing completely the feedback input of the controller circuit as soon the controller start supplying itself using at least one diode and any electronic switching system including low impedance switching voltage references able to provide a voltage higher in amount than the peak voltage at the feedback input.

34. A method for transfer of electrical energy between a low frequency AC power source and a complex load, the method comprising the steps of:

converting a signal from the AC power source into a low frequency fully rectified supply signal;

converting the low frequency fully rectified supply signal into a DC voltage across the complex load; and

providing a plurality of trains, wherein each train includes a plurality of pulses having a nearly constant duty cycle and frequency.

35. A system for transfer of electrical energy between a low frequency AC power source and a complex load, the system comprising:

a bridge rectifier circuit operatively connected to the AC power source for converting a signal from the AC power source into a low frequency fully rectified supply signal;

a complex load coupled to the bridge rectifier;

a boost converter unit operatively coupled to the bridge rectifier and the complex load for converting the low frequency fully rectified supply signal into a DC voltage across the complex load; and

a high frequency controller circuit coupled to the boost converter for providing a plurality of trains, wherein each train includes a plurality of pulses having a nearly constant duty cycle and frequency.

36. The system of claim 35 wherein the bridge rectifier is a four diode bridge rectifier having a negative output and a positive output.

37. The system of claim 36 wherein the complex load comprises at least one storage capacitive circuit having a positive end and a negative end and wherein the negative end of the complex load is coupled to the negative output of the bridge rectifier.

38. The system of claim 35 wherein the DC voltage across the complex load is higher in amount than the bridge rectifier peak voltage amount for eliminating any direct current between the bridge rectifier and the complex load.

39. The system of claims 38 wherein the boost converter unit is a controllable high frequency pulse width modulation boost converter unit.

40. The system of claim 39 wherein the boost converter unit comprises:

a capacitive circuit coupled across the output of the rectifier bridge, for having high impedance in respect to the AC power source low frequency supply signal and low impedance in respect to the boost converter high frequency signal;

a high frequency rectifier diode coupled to the complex load, wherein the high frequency rectifier diode includes;

an anode; and

a cathode, wherein the cathode of the high frequency rectifier diode is coupled to the positive end of the complex load;

an oscillating inductor coupled at one end to the positive output of the bridge rectifier and at the other end to the anode of the high frequency rectifier diode, wherein the inductor includes;

a charging time; and

a discharging time; and

a controllable power switch circuit coupled at one end to the oscillating inductor and the anode of the high frequency rectifier diode and at the other end to the negative pole of the bridge rectifier for periodically charging the oscillating inductor.

41. The system of claim 40 wherein the oscillating inductor is properly sized so that the momentary current amount across the inductor increases in direct proportional with its supply voltage and/or its charging time amount and for delivering to the complex load a high frequency pulse large signal during its discharging time.

42. The system of claim 41 wherein periodically charging of the oscillating inductor is in accordance with a high frequency driving pulse signal.

43. The system of claim 40 wherein the high frequency controller circuit provides the controllable switch with a proper driving pulse signal comprising trains of pulses that are constant in frequency and duty cycle during a time so that the current amount absorbed by the boost converter from the AC power source is contingent and linearly proportional to the AC power source supply signal voltage when the amount of the voltage amount across the complex load is maintained higher than the bridge rectifier peak voltage amount.

44. The system of claim 43 wherein the time of driving the trains of pulses is equal to one semi-cycle period of the AC power source supply waves.

45. The system of claim 44 wherein the time of driving the trains of pulses is longer than one semi-cycle period of the AC power source supply waves.

46. The system of claim 45 wherein the complex load comprises at least one storage capacitive circuit having a positive end and a negative end and wherein the negative end of the complex load is coupled to the positive output of the bridge rectifier.

47. The system of claim 35 wherein the boost converter unit is a controllable high frequency pulse width modulation buck-boost converter.

48. The system of claim 47 wherein the buck-boost converter comprises:

a capacitive circuit coupled across the output of the rectifier bridge, properly sized for having high impedance in respect to the AC power source low frequency supply signal and low impedance in respect to the boost converter high frequency signal.

a high frequency rectifier diode having an anode and a cathode and the cathode of the high frequency rectifier diode is coupled to the positive end of the complex load;

an oscillating inductor coupled at one end to the positive output of the bridge rectifier and at the other end to the anode of the high frequency rectifier diode, the inductor having a charging time and a discharging time and the inductor being properly sized so that the momentary current amount across the inductor increases linearly and direct proportional with its supply voltage and/or its charging time amount, for delivering to the complex load a high frequency pulse large signal during its discharging time; and

a controllable power switch circuit coupled at one end to the oscillating inductor and the anode of the high frequency rectifier diode and the switch is coupled at the other end to the negative pole of the bridge rectifier for being able to periodically charge the oscillating inductor in accordance to a high frequency driving pulse signal.

49. The system of claim 35, wherein the boost converter is a controllable high frequency pulse width modulation high efficiency snubber boost converter unit.

50. The system of claim 49 wherein the snubber boost converter unit comprises:

a first capacitive circuit coupled across the output of the rectifier bridge, properly sized for having high impedance in respect to the AC power source low frequency supply signal and low impedance in respect to the boost converter high frequency signal;

a first high frequency rectifier diode having an anode and a cathode and the cathode of the high frequency rectifier diode is coupled to the positive end of the complex load;

a second high frequency rectifier diode having an anode and a cathode and the cathode of the high frequency rectifier diode is coupled to the positive end of the complex load;

a third high frequency rectifier diode having an anode and a cathode and the anode of the high frequency rectifier diode is coupled to the positive output of the bridge rectifier;

a first oscillating inductor coupled at one end to the positive output of the bridge rectifier and at the other end to the anode of the first high frequency rectifier diode, the inductor having a charging time and a discharging time and the inductor being properly sized so that the momentary current amount across the inductor increases linearly and direct proportional with its supply voltage and/or its charging time amount, for delivering to the complex load a high frequency pulse large signal during its discharging time;

a second oscillating inductor coupled at one end to the cathode of the third high frequency rectifier diode and at the other end to the anode of the second high frequency rectifier diode, the inductor having a charging time and a discharging time and the inductor being properly sized so that the momentary current amount across the inductor increases linearly and direct proportional with its supply voltage and/or its charging time amount, for delivering to the complex load a high frequency pulse large signal during its discharging time;

a controllable power switch circuit having alternatively a ON and a OFF state coupled at one end to the first oscillating inductor and the anode of the first high frequency rectifier diode and the switch is coupled at the other end to the negative pole of the bridge rectifier for being able to periodically charge during its ON state the oscillating inductors in accordance to a high frequency driving pulse signal; and

a second capacitive circuit coupled at one end to the first inductor, the switch and the anode of the first high frequency rectifier diode and coupled at the other and to the second inductor and the second high frequency rectifier diode, properly sized for increasing the efficiency of the converter by not allowing a too fast increased of the switch'"'"'s voltage during its OFF period and the second capacitive circuit being also properly sized to do not negatively affect the high efficiency snubber converter circuit'"'"'s linearity in respect to the average current absorbed from the AC generator.

51. The system of claim 35 wherein the bridge rectifier includes a common output and wherein the complex load includes a three-terminal complex load having a positive end, a negative end and a common end, wherein the common end is coupled to the common output of the bridge rectifier circuit to form the common connection of the power factor correction system.

52. The method of claim 51 wherein the complex load comprises:

a first storage capacitive circuit coupled across the positive end and the common end of the three-terminal complex load;

a second storage capacitive circuit coupled across the negative end and the common end of the three-terminal complex load; and

a resistive circuit coupled across the positive end and the negative end of the three-terminal complex load.

53. The method of claim 35 wherein the boost converter unit includes a controllable high frequency pulse width modulation voltage doubler boost converter circuit operatively coupled to the bridge rectifier and the complex load for converting the low frequency fully rectified supply signal into a DC voltage across the complex load higher in amount than the bridge rectifier peak voltage amount for eliminating any direct current between the bridge rectifier and the complex load.

54. The method of claim 53 wherein the boost converter further comprises:

a first capacitive circuit coupled across the positive output and the common output of the bridge rectifier,

a second capacitive circuit coupled across the negative output and the common output of the bridge rectifier, wherein the first and second capacitive circuit each have a high impedance relative to the AC power source low frequency supply signal and a low impedance relative to the boost converter high frequency signal;

a first high frequency rectifier diode having an anode and a cathode wherein the cathode of the first high frequency rectifier diode is coupled to the positive end of the complex load;

a second high frequency rectifier diode having an anode and a cathode wherein the anode of the second high frequency rectifier diode is coupled to the negative end of the complex load;

a first oscillating inductor coupled at one end to the positive output of the bridge rectifier and at the other end to the anode of the first high frequency rectifier diode;

a second oscillating inductor coupled at one end to the negative output of the bridge rectifier and at the other end to the cathode of the second high frequency rectifier diode;

a first controllable power switch circuit coupled at one end to the first oscillating inductor and the anode of the first high frequency rectifier diode and the first controllable switch is coupled at the other end to the common output of the bridge rectifier and also coupled to the common end of the three terminals load for being able to periodically charge the first oscillating inductor in accordance to a high frequency driving pulse signal;

a second controllable power switch circuit coupled at one end to the second oscillating inductor and the cathode of the second high frequency rectifier diode and the second controllable switch is coupled at the other end to the common output of the bridge rectifier and also coupled to the common end of the three terminals load for being able to periodically charge the second oscillating inductor in accordance to a high frequency driving pulse signal;

a high frequency driving transformer comprising;

a primary coil able to directly receive and transfer simultaneously via magnetic field a pulse width modulation driving pulse signal to the first and second controllable switches;

a first secondary coil operatively connected to the first controllable switch; and

a second secondary coil operatively connected to the second controllable switch.

55. The system of claim 53, wherein the first inductor includes a charging time and a discharging time and wherein the momentary current amount across the first inductor increases linearly and in direct proportion with its supply voltage or its charging time amount, for delivering to the three terminals of the complex load a high frequency pulse large signal during its discharging time.

56. The system of claim 54, wherein the first inductor includes a charging time and a discharging time and wherein the momentary current amount across the first inductor increases linearly and in direct proportion with its supply voltage and its charging time amount, for delivering to the three terminals of the complex load a high frequency pulse large signal during its discharging time.

57. The method of claim 54, wherein the second inductor includes a charging time and a discharging time and wherein the momentary current amount across the second inductor increases linearly and in direct proportional with its supply voltage or its charging time amount, for delivering to the three terminals complex load a high frequency pulse large signal during its discharging time.

58. The method of claim 54, wherein the second inductor includes a charging time and a discharging time and wherein the momentary current amount across the second inductor increases linearly and in direct proportional with its supply voltage and its charging time amount, for delivering to the three terminals complex load a high frequency pulse large signal during its discharging time.

59. An apparatus for improving power factor correction to near unity comprising a high frequency controller circuit coupled between a low frequency AC power source and a complex load, the apparatus comprising means for generating a plurality of trains, wherein each train includes a plurality of pulses having a nearly constant duty cycle and frequency during a time at least equal to one semi-cycle period of a supply signal of the AC power source.

60. A method for power factor correction comprising the steps of

fully rectifying a low frequency AC power source signal,

controlling the fully rectified signal by pulse width modulation through the use of a pulse width modulation control signal comprises a train of pulses having a substantially constant frequency and a substantially constant duty cycle, and using a high frequency converter into a rectified high frequency supply signal, and

applying the resulting DC signal to a complex load where the load has a capacitive storage component.

61. The method of claim 60 further including the step of providing a DC/DC converter wherein current absorbed by the DC/DC converter from the AC power source is contingent upon and linearly proportional to the voltage of the AC power source signal.

62. A method for analog reset for improving the performances of mixed signal circuits and for achieving a smooth control of shorter output pulses from voltage mode pulse width modulators wherein the commutation speed of the analog comparator is lower than speed of an associated logic gate, the method comprising the steps of:

generating a voltage ramp signal and at least one synchronized square wave signal;

buffering the voltage ramp signal using the voltage ramp driving circuit;

comparing the voltage ramp signal with a reference voltage;

outputting a variable duty cycle square wave using a comparator circuit;

securing an output pulse per cycle of the voltage ramp signal using a three NOR gate pulse width modulation logic circuit;

resetting the output logic state of the pulse width modulation logic circuit during each cycle of the voltage ramp signal using a synchronized signal

63. The method of claim 62 wherein the synchronized signal comes from an oscillator circuit.

64. The method of claim 62 wherein the synchronized signal comes from the pulse width modulation circuit.

65. The method of claim 62 further comprising the step of providing to the comparator circuit, directly from the oscillator, a modified voltage ramp signal having its amplitude near zero during its descendent period, thereby eliminating the need of a voltage ramp driver circuit and/or synchronized square wave signal.

66. A method of non-linear correction comprising the steps of:

adapting the shape of current absorbed by a controllable converter circuit from an AC power source; and

reducing periodically the duty cycle ratio of the driving signal provided by a pulse width modulation controller circuit wherein the step of reducing includes;

altering a first voltage with a portion of a second voltage; and

proportionally altering the controllable converter circuit'"'"'s driving pulses'"'"' duty cycle.

67. The method of claim 66 wherein the controller circuit includes an operational amplifier including a feedback input, a reference input, and a compensation output operatively connected for decreasing the duty cycle ratio of a driving output that provides a pulse width modulation signal to the controllable converter circuit during the time when the AC power source'"'"'s momentarily voltage amount is higher than a pre-established amount.

68. The method of claim 67 further comprising the steps of:

sensing the AC power source'"'"'s supply signal using a resistive divider circuit connected to one input of the operational amplifier;

comparing said AC power source'"'"'s supply signal amount to a reference voltage coupled to the other input of the operational amplifier; and

decreasing periodically the duty cycle ratio of the driving output signal only when the AC power source'"'"'s supply signal amount is higher that a pre-established reference using a proper gain and compensation circuit for the operational amplifier.