Duty cycle correction circuit of delay locked loop and the delay locked loop having the duty cycle correction circuit

• US 20050212575A1
• Filed: 05/16/2005
• Published: 09/29/2005
• Est. Priority Date: 05/22/2003
• Status: Active Grant

• Current Assignee: Youn-Cheul Kim
• Original Assignee: Youn-Cheul Kim
• Inventors: Kim, Youn-cheul
• Granted Patent: US 7,202,720 B2
• Time in Patent Office: Days
• US Class Current: 327/158
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Claims

1. A delay locked loop comprising:

a DLL core, which receives an external clock signal and generates an internal clock signal synchronized to the external clock signal;

a buffer, which buffers the internal clock signal and outputs differential reference clock signals; and

a duty cycle correction circuit, which generates duty rate control signals each having a predetermined offset corresponding to a difference of respective duty cycles of the differential reference clock signals; and

a control signal generation circuit, which generates switching control signals for controlling the offset, and outputs the switching control signals to the duty cycle correction circuit,

wherein the DLL core corrects a duty cycle of the internal clock signal, in response to the duty rate control signals.

2. The delay locked loop of claim 1, wherein the duty cycle correction circuit comprises:

a differential amplifier, which receives and amplifies the differential reference clock signals through a first input terminal and a second input terminal, and outputs differential output signals to a first differential output terminal and a second differential output terminal, respectively;

a first transmission circuit, which is connected between the first differential output terminal and a first node, and transmits a signal of the first differential output terminal to the first node, in response to transmission control signals;

a second transmission circuit, which is connected between the second differential output terminal and a second node, and transmits a signal of the second differential output terminal to the second node, in response to the transmission control signals;

a first storage unit, which is connected between the first node and a ground voltage and accumulates electric charges on the first node;

a second storage unit, which is connected between the second node and the ground voltage and accumulates electric charges on the second node; and

a control circuit, which controls an amount of electric charges accumulated in the first storage unit and an amount of electric charges accumulated in the second storage unit, in response to corresponding switching control signals.